ADSP-2191MKSTZ-160 Analog Devices Inc, ADSP-2191MKSTZ-160 Datasheet - Page 27

• Manufacturer Part Number: ADSP-2191MKSTZ-160
• Description: IC DSP CONTROLLER 16BIT 144LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2191MKSTZ-160

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 16 Bit
• Frequency: 160MHz
• Supply Voltage: 3.3V
• Embedded Interface Type: HPI, SPI, UART
• No. Of I/o's: 16
• No. Of Mips: 160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Port ACC Mode Write Cycle Timing
Table 16
Address Cycle Control (ACC) mode. For more information on
ACK, Ready, ALE, and ACC mode selection, see the Host port
modes description
Table 16. Host Port ACC Mode Write Cycle Timing
1
2
REV. A
t
Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent
Parameter
Switching Characteristics
t
t
t
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NH
at the same time.
on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
WHKS1
WHKS2
WHKH
WHS
WHH
WSHKS
WHHKH
WAL
CSAL
ALCS
WCSW
ALW
CSW
WCS
ALEW
HKWD
ADW
WAD
DWS
WDH
HKWAL
are peripheral bus latencies (n t
and
Figure 15
HWR Asserted to HACK Asserted (ACK Mode) First Byte
HWR Asserted to HACK Asserted (Setup, ACK Mode)
HWR Deasserted to HACK Deasserted (Hold, ACK Mode)
HWR Asserted to HACK Asserted (Setup, Ready Mode)
HWR Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
HWR Asserted to HACK Asserted (Setup) During Address
Latch
HWR Deasserted to HACK Deasserted (Hold) During
Address Latch
HWR Asserted to HALE Deasserted (Delay)
HCMS or HCIOMS Asserted to HALE Asserted (Delay)
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
HWR Deasserted to HCMS or HCIOMS Deasserted
HALE Asserted to HWR Asserted
HCMS or HCIOMS Asserted to HWR Asserted
HWR Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Write)
HALE Deasserted to HWR Asserted
HACK Asserted to HWR Deasserted (Hold, ACK Mode)
Address Valid to HWR Asserted (Setup)
HWR Deasserted to Address Invalid (Hold)
Data Valid to HWR Deasserted (Setup)
HWR Deasserted to Data Invalid (Hold)
HACK Asserted to HWR Deasserted (Hold) During Address
Latch
on Page
2
describe Host port write operations in
8.
HCLK
); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory
–27–
2
Min
10
0
1.5
0
1
0
0.5
0
0
1
1.5
3
3
2
2
2
ADSP-2191M
Max
5t
12
10
10
5t
10
10
HCLK
HCLK
+t
+t
NH
NH
1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns