ADSP-21061KS-133 Analog Devices Inc, ADSP-21061KS-133 Datasheet - Page 41

• Manufacturer Part Number: ADSP-21061KS-133
• Description: IC DSP CONTROLLER 32BIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061KS-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Frequency: 33MHz
• Supply Voltage: 5V
• Embedded Interface Type: HPI, Serial
• No. Of Mips: 50
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RCLK
TCLK
RFS
TFS
DR
DT
TFS, RFS, DT
TCLK, RCLK
RCLK (INT)
TCLK (INT)
TCLK
TCLK
(EXT)
(INT)
t
t
CLKIN
HOFSE
HOFSI
t
DATA TRANSMIT— INTERNAL CLOCK
HDTI
DATA RECEIVE— INTERNAL CLOCK
DT
DT
DRIVE
DRIVE
EDGE
EDGE
DRIVE EDGE
SPORT DISABLE DELAY
FROM INSTRUCTION
t
t
DFSE
t
DDTI
DRIVE
EDGE
DFSI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTEN
t
t
SCLKIW
SCLKIW
t
LOW TO HIGH ONLY
DCLK
t
t
DPTR
DDTIN
t
t
t
SFSI
SDRI
SFSI
SAMPLE
SAMPLE
EDGE
EDGE
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
Rev. C | Page 41 of 56 | July 2007
t
t
t
HFSI
HFSI
HDRI
Figure 24. Serial Ports
TFS (EXT)
TCLK/RCLK
TCLK/RCLK
CLKIN
RCLK
TCLK
RFS
TFS
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
DR
DT
t
t
HOFSE
HOFSE
t
HDTE
DATA TRANSMIT— EXTERNAL CLOCK
DRIVE
DRIVE
EDGE
EDGE
DATA RECEIVE— EXTERNAL CLOCK
DRIVE EDGE
DRIVE
EDGE
t
STFSCK
t
t
t
DFSE
DFSE
DDTE
t
DDTTE
ADSP-21061/ADSP-21061L
t
t
t
HTFSCK
SCLKW
SCLKW
t
DDTTI
t
t
t
SFSE
SDRE
SFSE
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HDRE
HFSE
HFSE