KMSC8126VT8000 Freescale Semiconductor, KMSC8126VT8000 Datasheet - Page 4

• Manufacturer Part Number: KMSC8126VT8000
• Description: DSP 16BIT QUAD 500MHZ 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8126VT8000

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 500MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Device Core Size: 16b
• Clock Freq (max): 500MHz
• Mips: 500
• Device Input Clock Speed: 500MHz
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Temp Range: 0C to 90C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 431
• Package Type: FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Features
4
Memory Controller
60x-Compatible
Interface (DSI)
3-Mode Signal
Multiplexing
System Bus
Direct Slave
Feature
• 64/32-bit data and 32-bit address 60x bus.
• Support for multiple-master designs.
• Four-beat burst transfers (eight-beat in 32-bit wide mode).
• Port size of 64, 32, 16, and 8 controlled by the internal memory controller.
• Bus can access external memory expansion or off-device peripherals, or it can enable an external
• Slave support, direct access by an external host to internal resources including the M1 and M2
• On-device arbitration between up to four master devices.
A 32/64-bit wide slave host interface that operates only as a slave device under the control of an
external host processor.
• 21–25 bit address, 32/64-bit data.
• Direct access by an external host to internal and external resources, including the M1 and the M2
• Synchronous and asynchronous accesses, with burst capability in the synchronous mode.
• Dual or Single strobe modes.
• Write and read buffers improve host bandwidth.
• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.
• Sliding window mode enables access with reduced number of address pins.
• Chip ID decoding enables using one CS signal for multiple DSPs.
• Broadcast CS signal enables parallel write to multiple DSPs.
• Big-endian, little-endian, and munged little-endian support.
• 64-bit DSI, 32-bit system bus.
• 32-bit DSI, 64-bit system bus.
• 32-bit DSI, 32-bit system bus, and Ethernet.
Flexible eight-bank memory controller:
• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a
• Glueless interface to SRAM, 133 MHz page mode SDRAM, DRAM, EPROM, Flash memory, and
• Byte enables for either 64-bit or 32-bit bus width mode.
• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control
host device to access internal resources.
memories.
memories as well as external devices on the system bus.
page-mode SDRAM machine.
other user-definable peripherals.
IPBus peripherals and internal memories. Each bank has the following features:
— 32-bit address decoding with programmable mask.
— Variable block sizes (32 KB to 4 GB).
— Selectable memory controller machine.
— Two types of data errors check/correction: normal odd/even parity and read-modify-write
— Write-protection capability.
— Control signal generation machine selection on a per-bank basis.
— Support for internal or external masters on the system bus.
— Data buffer controls activated on a per-bank basis.
— Atomic operation.
— RMW data parity check (on system bus only).
— Extensive external memory-controller/bus-slave support.
— Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the
— Data pipeline to reduce data set-up time for synchronous devices.
(RMW) odd/even parity for single accesses.
system bus only).
Table 3. Buses and Memory Controller
MSC8126 Product Brief, Rev. 7
Description
Freescale Semiconductor