XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 14

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Table 16: Processor Block Switching Characteristics
Table 17: Processor Block PLB Switching Characteristics
Table 18: Processor Block JTAG Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Setup and Hold Relative to Clock (CPMC405CLOCK)
Clock to Out
Clock
Setup and Hold Relative to Clock (PLBCLK)
Clock to Out
Setup and Hold Relative to Clock (JTAGC405TCK)
Clock to Out
Clock and Power Management control inputs
Reset control inputs
Debug control inputs
Trace control inputs
External Interrupt Controller control inputs
Clock and Power Management control outputs
Reset control outputs
Debug control outputs
Trace control outputs
CPMC405CLOCK minimum pulse width, High
CPMC405CLOCK minimum pulse width, Low
Processor Local Bus (ICU/DCU) control inputs
Processor Local Bus (ICU/DCU) data inputs
Processor Local Bus (ICU/DCU) control outputs
Processor Local Bus (ICU/DCU) address bus outputs
Processor Local Bus (ICU/DCU) data bus outputs
JTAG control inputs
JTAG reset input
JTAG control outputs
Description
Description
Description
T
T
T
T
T
PPCDCK
PPCCKD
PPCDCK
PPCCKD
PPCCKO
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PPCDCK
PPCCKD
PPCDCK
PPCCKD
PPCDCK
PPCCKD
PPCDCK
PPCCKD
PPCDCK
PPCCKD
PPCCKO
PPCCKO
PPCCKO
PPCCKO
CPWH
CPWL
_JTGTDI
_JTGTDI
_JTGTRSTN
_JTGTRSTN
_JTGTDO
Symbol
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T
T
T
T
T
T
T
Symbol
_CORECKI/
_CORECKI
_RSTCHIP/
_RSTCHIP
_EXBUSHAK/
_EXBUSHAK
_TRCDIS/
_TRCDIS
_CINPIRQ/
_CINPIRQ
_CORESLP
_RSTCHIP
_DBGLDAPU
_TRCCYCLE
PPCCKO
PPCDCK
PPCCKD
PPCDCK
PPCCKD
PPCCKO
PPCCKO
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Symbol
_DCUWRDBUS
_ICUBUSY/
_ICUBUSY
_ICURDDB/
_ICURDDB
_DCUABORT
_ICUABUS
0.60
0.20
0.60
0.20
0.60
0.20
0.60
0.20
1.04
0.20
1.35
1.44
1.34
1.52
1.11
1.11
1.68
-12
1.16
0.20
0.60
0.20
-12
0.60
0.20
0.90
0.20
1.61
1.66
2.08
-12
Speed Grade
Speed Grade
Speed Grade
0.65
0.20
0.65
0.20
0.65
0.20
0.65
0.20
1.15
0.20
1.59
1.48
1.68
1.25
1.25
1.51
1.79
1.29
0.20
0.65
0.20
-11
-11
0.66
0.20
1.00
0.20
1.78
1.85
2.24
-11
0.74
0.23
0.74
0.23
0.74
0.23
0.74
0.23
1.40
0.23
1.74
1.83
1.70
1.83
1.43
1.43
1.48
0.23
0.74
0.23
2.14
-10
-10
0.76
0.23
1.15
0.23
2.05
2.13
2.57
-10
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
Units
Units
14