EP1S10F672C7N Altera, EP1S10F672C7N Datasheet - Page 108

• Manufacturer Part Number: EP1S10F672C7N
• Description: IC STRATIX FPGA 10K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F672C7N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 345
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1851; EP1S10F672C7N

PLLs & Clock Networks
2–94
Stratix Device Handbook, Volume 1
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
pair of output pins (four pins total) has dedicated VCC and GND pins to
reduce the output clock’s overall jitter by providing improved isolation
from switching I/O pins.
For PLLs 5 and 6, each pin of a single-ended output pair can either be in
phase or 180° out of phase. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as
well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology,
differential HSTL, and differential SSTL.
standards the enhanced PLL clock pins support. When in single-ended or
differential mode, the two outputs operate off the same power supply.
Both outputs use the same standards in single-ended mode to maintain
performance. You can also use the external clock output pins as user
output pins if external enhanced PLL clocking is not needed.
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5-V HSTL Class I
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
I/O Standard
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 2–20
Input
PLLENABLE
shows which I/O
v
v
Altera Corporation
EXTCLK
July 2005
Output
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v