EP20K300EFC672-2 Altera, EP20K300EFC672-2 Datasheet - Page 7

IC APEX 20KE FPGA 300K 672-FBGA

EP20K300EFC672-2

Manufacturer Part Number
EP20K300EFC672-2
Description
IC APEX 20KE FPGA 300K 672-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K300EFC672-2

Number Of Logic Elements/cells
11520
Number Of Labs/clbs
1152
Total Ram Bits
147456
Number Of I /o
408
Number Of Gates
728000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP20K300EFC672-2
Manufacturer:
ALTERA
Quantity:
18
Part Number:
EP20K300EFC672-2
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP20K300EFC672-2
Manufacturer:
ALTERA
0
Part Number:
EP20K300EFC672-2N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP20K300EFC672-2N
Manufacturer:
ALTERA
0
Part Number:
EP20K300EFC672-2X
Manufacturer:
ALTERA
Quantity:
329
Part Number:
EP20K300EFC672-2X
Manufacturer:
ALTERA
0
Part Number:
EP20K300EFC672-2X
Manufacturer:
ALTERA
Quantity:
15
Altera Corporation
MultiCore system integration
SignalTap logic analysis
32/64-Bit, 33-MHz PCI
32/64-Bit, 66-MHz PCI
MultiVolt I/O
ClockLock support
Dedicated clock and input pins Six
I/O standard support
Memory support
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
Full support
Full support
Full compliance in -1, -2 speed
grades
2.5-V or 3.3-V V
V
Certain devices are 5.0-V tolerant
Clock delay reduction
2× and 4× clock multiplication
2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
Low-voltage transistor-to-transistor
logic (LVTTL)
Dual-port RAM
FIFO
RAM
ROM
CCIO
selected for device
APEX 20K Devices
CCIO
APEX 20K Programmable Logic Device Family Data Sheet
-
Full compliance in -1, -2 speed grades
Full compliance in -1 speed grade
1.8-V, 2.5-V, or 3.3-V V
V
5.0-V tolerant with use of external resistor
Clock delay reduction
m /(n × v) or m /(n × k) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Eight
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
GTL+
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
(in EP20K300E and larger devices)
LVDS and LVPECL signaling (in all BGA
and FineLine BGA devices)
LVDS and LVPECL data pins up to
156 Mbps (in -1 speed grade devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
CAM
Dual-port RAM
FIFO
RAM
ROM
Full support
Full support
CCIO
selected block-by-block
APEX 20KE Devices
CCIO
7

Related parts for EP20K300EFC672-2