EP2S30F484I4N Altera, EP2S30F484I4N Datasheet - Page 10

IC STRATIX II FPGA 30K 484-FBGA

EP2S30F484I4N

Manufacturer Part Number
EP2S30F484I4N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S30F484I4N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
342
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1894
EP2S30F484I4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S30F484I4N
Manufacturer:
FREESCALE
Quantity:
101
Part Number:
EP2S30F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F484I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S30F484I4N
Manufacturer:
ALTERA
0
Part Number:
EP2S30F484I4N
Manufacturer:
ST
0
Part Number:
EP2S30F484I4N
Manufacturer:
ALTERA
Quantity:
300
Part Number:
EP2S30F484I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2S30F484I4N
0
Functional Description
Figure 2–1. Stratix II Block Diagram
2–2
Stratix II Device Handbook, Volume 1
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
transfer at up to 1 Gbps using LVDS or HyperTransport
standards.
Figure 2–1
DSP
Block
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
shows an overview of the Stratix II device.
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
LVDS, HyperTransport & other
I/O Standards
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
M-RAM Block
TM
Altera Corporation
LABs
LABs
LABs
LABs
technology I/O
LABs
LABs
LABs
LABs
May 2007

Related parts for EP2S30F484I4N