EP2S180F1020C3N Altera, EP2S180F1020C3N Datasheet - Page 135

• Manufacturer Part Number: EP2S180F1020C3N
• Description: IC STRATIX II FPGA 180K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1020C3N

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1883; EP2S180F1020C3N; Q2675539B

Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
Notes to
(1)
(2)
Power-On Reset
Circuitry
Altera Corporation
May 2007
This is the logic array signal or the larger of either the V
This is the larger of either the V
Figure
4–2:
n+
Logic Array
Stratix II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the V
levels and tri-states all the user I/O pins while V
normal user levels are reached. The POR circuitry also ensures that all
eight I/O bank V
V
triggered. After the Stratix II device enters user mode, the POR circuit
continues to monitor the V
condition during user mode can be detected. If there is a V
sag below the Stratix II operational level during user mode, the POR
circuit resets the device.
When power is applied to a Stratix II device, a power-on-reset event
occurs if V
period of time (specified as a maximum V
V
dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms
during power-up. When the PORSEL pin is connected to ground, the POR
time is 100 ms. When the PORSEL pin is connected to V
is 12 ms.
p-well
Signal
CCINT
CC
CCIO
rise time for Stratix II device is 100 ms. Stratix II devices provide a
voltage, reach an acceptable level before configuration is
or V
n+
CC
PAD
reaches the recommended operating range within a certain
signal.
V
CCIO
PAD
voltages, V
CCIO
p+
CCINT
or V
PAD
(1)
voltage level so that a brown-out
CCPD
signal.
Stratix II Device Handbook, Volume 1
n-well
voltage, as well as the logic array
V
CCIO
p+
Hot Socketing & Power-On Reset
CCINT
CC
rise time). The maximum
, V
(2)
n+
CC
CCIO
p-substrate
is ramping up until
, and V
CC
, the POR time
CCINT
CCPD
voltage
voltage
4–5