EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 65

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–43. DPA Lock Time Specifications—Stratix IV GX and GT Devices Only
Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than
1.25 Gbps
April 2011 Altera Corporation
SPI-4
Parallel Rapid I/O
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Standard
Table
1–43:
0.35
8.5
25
0.1
F1
Table 1–43
Figure 1–5
a data rate equal to or higher than 1.25 Gbps.
form.
00000000001111111111
F2
Training Pattern
00001111
10010000
10101010
01010101
shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
lists the DPA lock time specifications for Stratix IV GX and GT devices.
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
Transitions in One
Repetition of the
Training Pattern
Number of Data
Jitter Frequency (Hz)
2
2
4
8
8
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
F3
Table 1–44
per 256 Data Transitions
Number of Repetitions
(Note
128
128
64
32
32
(4)
1), (2),
lists this information in table
(3)
F4
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Maximum
1–57

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