EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 63

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–41. High-Speed I/O Specifications
April 2011 Altera Corporation
TCCS
Receiver
True Differential I/O
Standards -
f
f
DPA Mode
DPA run length
Soft CDR mode
Soft-CDR PPM
tolerance
Non DPA Mode
Sampling Window
Notes to
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum and maximum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global,
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
HSDRDPA
HSDR
regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(data rate)
Symbol
Table
(data rate)
1–41:
1
True Differential I/O Standards
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
SERDES factor J = 3 to 10
SERDES factor J = 3 to 10
Emulated Differential I/o
Uses an SDR Register
SERDES factor J = 2,
SERDES factor J = 1,
Uses DDR Registers
Conditions
Standards
—
—
—
(Note 1), (2), (10)
–2/–2× Speed Grade
Min
150
—
—
—
—
—
(4)
(4)
(4)
Typ
—
—
—
—
—
—
—
—
—
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
(Part 3 of 3)—Preliminary
10000
1600
Max
100
250
300
300
(4)
(4)
(4)
Min
150
—
—
(4)
(4)
(4)
—
—
—
–3
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
10000
1250
Max
100
250
300
300
(4)
(4)
(4)
Min
150
—
—
—
—
—
(4)
(4)
(4)
–4
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
10000
1250
Max
100
250
300
300
(4)
(4)
(4)
1–55
Mbps
Mbps
Mbps
Mbps
PPM
Unit
ps
ps
UI
ps
±