XC5VLX85-2FFG1153C Xilinx Inc, XC5VLX85-2FFG1153C Datasheet - Page 90

• Manufacturer Part Number: XC5VLX85-2FFG1153C
• Description: IC FPGA VIRTEX-5 85K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX85-2FFG1153C

• Number Of Logic Elements/cells: 82944
• Number Of Labs/clbs: 6480
• Total Ram Bits: 3538944
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Phase-Locked Loops (PLLs)
X-Ref Target - Figure 3-1
90
From any IBUFG implementation
From any BUFG implementation
Phase Locked Loop (PLL)
Virtex-5 devices contain up to six CMT tiles. The PLLs main purpose is to serve as a
frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for
either external or internal clocks in conjunction with the DCMs of the CMT.
The PLL block diagram shown in
components.
X-Ref Target - Figure 3-2
Clock Pin
Figure 3-1: Block Diagram of the Virtex-5 FPGA CMT
Figure 3-2: Block Diagram of the Virtex-5 FPGA PLL
D
www.xilinx.com
PFD
Figure 3-2
DCM1
DCM2
PLL
M
CP
provides a general overview of the PLL
LF
clkout_pll<5:0>
VCO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
To any BUFG
implementation
To any BUFG
implementation
To any BUFG
implementation
UG190_c3_01_022709
O0
O1
O2
O3
O4
O5
ug190_3_02_030506