XC2V4000-5FFG1517C Xilinx Inc, XC2V4000-5FFG1517C Datasheet - Page 46

• Manufacturer Part Number: XC2V4000-5FFG1517C
• Description: IC FPGA VIRTEX-II 4M 1517-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V4000-5FFG1517C

• Number Of Labs/clbs: 5760
• Total Ram Bits: 2211840
• Number Of I /o: 912
• Number Of Gates: 4000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

ments to begin changing state in response to the logic and
the user clock.
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Readback
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary-Scan mode.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Platform FPGA User Guide.
Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
Revision History
This section records the change history for this module of the data sheet.
DS031-2 (v3.5) November 5, 2007
Product Specification
11/07/00
12/06/00
01/15/01
01/25/01
04/02/01
07/30/01
10/02/01
10/12/01
11/29/01
Date
R
Version
1.0
1.1
1.2
1.3
1.5
1.6
1.7
1.8
1.9
Early access draft.
Initial release.
Added values to the tables in the
Switching Characteristics
The data sheet was divided into four modules (per the current style standard). A note was
added to
•
•
•
•
•
•
•
•
Under
pull-down resistors was changed to 10 - 60 KΩ from 50 - 100 KΩ.
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
Added Table 6.
Changed definition of multiply and divide integer ranges under
(DCM).
Made numerous minor edits throughout this module.
Updated descriptions under
Multiplexer
Made clarifying edits under
Changed bitstream lengths for each device in
Table
Input/Output Individual
1.
Buffers,
www.xilinx.com
Digital Clock Manager
sections.
Digital Clock Manager
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II Platform FPGA User Guide. For
devices that support this feature, please contact your sales
representative for specific ordering part number.
Partial Reconfiguration
Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration “frame” of the bitstream (device size depen-
dent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
Digitally Controlled Impedance
Virtex-II Performance Characteristics
Options, the range of values for optional pull-up and
Virtex-II Platform FPGAs: Functional Description
Revision
(DCM), and
Table
(DCM).
26.
Creating a
(DCI),
Digital Clock Manager
Design.
Global Clock
and
BATT
Virtex-II
pin, when the
Module 2 of 4
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