XCV812E-7FG900C Xilinx Inc, XCV812E-7FG900C Datasheet - Page 55

• Manufacturer Part Number: XCV812E-7FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-7FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 44:
Revision History
The following table shows the revision history for this document.
DS025-2 (v2.3) November 19, 2002
IOBUFDS_LD_LVDS
IOBUFDS_LDE_LVDS
IOBUFDS_LDC_LVDS
IOBUFDS_LDCE_LVDS
IOBUFDS_LDP_LVDS
IOBUFDS_LDPE_LVDS
03/23/00
08/01/00
09/19/00
11/20/00
04/02/01
04/19/01
07/23/01
11/16/01
07/17/02
09/10/02
11/19/02
Date
R
Bidirectional I/O Library Macros (Continued)
Version
Name
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2.0
2.1
2.2
2.3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Initial Xilinx release.
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum T
In
and pin G16 is now labeled as VREF.
Updated values in
Converted data sheet to modularized format.
Modified
Made minor edits to text under Configuration.
Added warning under
bitstream causes configuration to fail and can damage the device.
Data sheet designation upgraded from Preliminary to Production.
Added clarifications in the
and
Added clarification in the
Removed last sentence regarding deactivation of duty-cycle correction in
Correction Property
Table
Block SelectRAM+ Memory
4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,
Figure
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
30, which shows “DLL Generation of 4x Clock in Virtex-E Devices.”
D, T, GE, G, CLR
D, T, GE, G, PRE
Virtex-E Switching Characteristics
www.xilinx.com
1-800-255-7778
D, T, G, PRE
section.
D, T, G, CLR
DLLPW
D, T, GE, G
Configuration
Inputs
D, T, G
Boundary Scan
Input/Output
in -6 speed grade for DLL Timing Parameters (Module 3).
sections. Revised
section that attempting to load an incorrect
Revision
Block, Configuration,
section.
Bidirectional
Figure
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
tables.
18,
Boundary-Scan
Table
11, and
Duty Cycle
Outputs
Module 2 of 4
Table
Q
Q
Q
Q
Q
Q
Mode,
36.
51