XC4010D-5PQ160C Xilinx Inc, XC4010D-5PQ160C Datasheet - Page 32

• Manufacturer Part Number: XC4010D-5PQ160C
• Description: IC LOGIC CL ARRAY 10K GAT 160PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010D-5PQ160C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Number Of I /o: 129
• Number Of Gates: 10000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 160-BQFP
• Case: QFP160
• Dc: 96+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1072

XC4000, XC4000A, XC4000H Logic Cell Array Families
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the LCA device(s). The first byte of parallel
configuration data must be available at the D inputs of the
lead LCA device a short set-up time before the rising CCLK
edge. Subsequent data bytes are clocked in on every
eighth consecutive rising CCLK edge. The same CCLK
edge that accepts data, also causes the RDY/BUSY
output to go High for one CCLK period. The pin name is a
misnomer. In Synchronous Peripheral mode it is really an
ACKNOWLEDGE signal. Synchronous operation does
not require this response, but it is a meaningful signal for
test purposes.
The lead LCA device serializes the data and presents the
preamble data ( and all data that overflows the lead device)
on its DOUT pin. There is an internal delay of 1.5 CCLK
periods, which means that DOUT changes on the falling
CCLK edge, and the next LCA device in the daisy-chain
accepts data on the subsequent rising CCLK edge. In
order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisy-
chained device.
REPROGRAM
DATA BUS
CONTROL
SIGNALS
CLOCK
5 k
+5 V
+5 V
RDY/BUSY
INIT
CCLK
D
PROGRAM
0-7
M0 M1
XC4000
2-38
I/O Pins
Other
DOUT
M2
HDC
LDC
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the PROGRAM input, or pull the
bidirectional INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27).
A Low on the PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode
by capturing its status inputs, and is ready to start the
configuration process. A master device waits an additional
max 250 s to make sure that all slaves in the potential
daisy-chain have seen INIT being High.
•
•
•
+5 V
GENERAL-PURPOSE
USER I/O PINS
OPTIONAL
DAISY-CHAINED
LCA DECVICES WITH
DIFFERENT
CONFIGURATIONS
X6079