CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 31

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watch Dog Reset
(bit 4 set) has occurred and no interrupts are pending (bit 7 clear).
19.0
Interrupts can be generated by the GPIO lines, the internal free-running timer, on various USB events, PS/2 activity, or by the
wake-up timer. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable
Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position. During a reset, the contents of the
interrupt enable registers are cleared, along with the Global Interrupt Enable bit of the CPU, effectively disabling all interrupts.
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 19-3 for the logic block diagram of the interrupt
controller. When an interrupt is generated it is first registered as a pending interrupt. It will stay pending until it is serviced or a
reset occurs. A pending interrupt will only generate an interrupt request if it is enabled by the corresponding bit in the interrupt
enable registers. The highest priority interrupt request will be serviced following the completion of the currently executing
instruction.
When servicing an interrupt, the hardware will first disable all interrupts by clearing the Global Interrupt Enable bit in the CPU (the
state of this bit can be read at Bit 2 of the Processor Status and Control Register). Next, the flip-flop of the current interrupt is
cleared. This is followed by an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e.,
the Interrupt Vector, see Section 19.1). The instruction in the interrupt table is typically a JMP instruction to the address of the
Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction.
Interrupts can be nested to a level limited only by the available stack space.
The Program Counter value and the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic CALL
instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used just before the RETI instruction to
restore the accumulator value. The program counter, CF and ZF are restored and interrupts are enabled when the RETI instruction
is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
19.1
The Interrupt Vectors supported by the device are listed in Table 19-1. The highest priority interrupt is #1 (USB Bus Reset / PS/2
activity), and the lowest priority interrupt is #11 (Wake-up Timer). Although Reset is not an interrupt, the first instruction executed
after a reset is at ROM address 0x0000, which corresponds to the first entry in the Interrupt Vector Table. Interrupt vectors occupy
2 bytes to allow for a 2-byte JMP instruction to the appropriate Interrupt Service Routine (ISR).
Table 19-1. Interrupt Vector Assignments
Document #: 38-08028 Rev. *B
Interrupt Vector Number
Interrupt Vectors
Interrupts
not applicable
10
11
1
2
3
4
5
6
7
8
9
FOR
FOR
ROM Address
0x000C
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000E
0x0010
0x0012
0x0014
0x0016
Execution after Reset begins here.
USB Bus Reset or PS/2 Activity interrupt
128-µs timer interrupt
1.024-ms timer interrupt
USB Endpoint 0 interrupt
USB Endpoint 1 interrupt
Reserved
Reserved
Reserved
Reserved
GPIO interrupt
Wake-up Timer interrupt
CY7C63221/31A
enCoRe™ USB
Function
Page 31 of 50
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