STA2058 STMicroelectronics, STA2058 Datasheet
STA2058
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STA2058 Summary of contents
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... Evaluation board hosting STA2058 module ■ SDK board (for application SW development) Description STA2058 is the high-sensitivity baseband of TESEO GPS platform which include the STA5620 RF Front-End. The embedded Flash memory enables the equipment manufacturer to load the entire GPS software (including tracking, acquisition, navigation and data output) after customizing its interfaces to his needs ...
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... DC electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 nRSTIN input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Flash electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9 GPS performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 STA2058 ...
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... Watchdog timer with 8 bits prescaler for system reliability and integrity. ● 2 CAN modules compliant with the CAN specification V2.0 part B (active) and bit rate can be programmed MBaud. One additional CAN at 1 Mbps (for STA2058 EM SIP version) ● Four 16-bit programmable timers with 7 bit prescaler two input capture/output compare, one pulse counter function, one PWM channel with selectable frequency each ...
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... USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume support ● High level data link controller (HDLC) unit supports full duplex operating mode, NRZ, NRZI, FM0 and MANCHESTER modes, and internal 8-bit baud rate generator. 4/ Interface is multiplexed with SPI + may be used at a time. STA2058 ...
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... STA2058 2 Pin description 2.1 Logic symbol Figure 1. STA2058 TESEO symbol Power Pads Clock & Reset JTAG Port Debug V18 (2) V33 (7) VSS (10) AVSS AVDD V18BKP GPSCLK CK STA2058 CKOUT TESEO RSTINn JTDI JTCK JTMS JTRSTn JTDO DBGRQS BOOTEN Pin description A[23:0] EMI D[15:0] Interface WEn ...
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... System block diagram 3 System block diagram Figure 2. STA2058 TESEO block diagram 6/20 ARM7TDMI CPU EMI 256K Flash APB BRIDGE3 64K RAM STC(JTAG) VREG APB BRIDGE2 RCCU PLL Interrupt Contr. 12-bit A/D Converter TIMER0 TIMER1 TIMER2 TIMER3 RTC OSCILL Wakeup WATCHDOG Fully Prog. ...
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... STA2058 Figure 3. New HPGPS 16-ch including Emerald DSP 16-bit (*) Maximum memory size addressable by HPGPS. The real value depends on the device specs pbus ybus pbus xbus ybus xbus 4 Register APB Interface INT ISR APB bus 3 HPGPS IP HPGPS_EME top System block diagram Acquisition ...
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... P1.8/ T3.OCMP D.9 NC PPS B/ AIN.0 P1.7/ P1.1/ P1.5/ T1.OCMP D.8 T3.ICAPA/ T1.ICAPB B AIN.1 P1.3/ VSSIO- P1.4/ D.5 T3.ICAPB/ PLL T1.ICAPA AIN.3 P1.6/ V33IO-PLL D.7 D.6 T1.OCMPA STA2058 M NC V33REG_B KP DBGRQS VSS P0.15/ WAKEUP RSTINn D.2 AVDD D.4 AVDD P1.2/ T3.OCMPA/ AIN.2 ...
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... STA2058 3.2 Package LQFP64 Figure 4. LQFP64 package outline P0.10/U1.RX/U1.TX P0.11/U1.TX/BOOT.1 P0.12/SCCLK P0.13/ U2.RX/T2.OCMPA P0.14/ U2.TX/T2.ICAPA VSS TESEO BOOTEN 7 LQFP64 VSS 8 V33 9 JTDI 10 JTMS 11 JTCK 12 JTDO 13 nJTRST 14 GPSDAT 15 GPSCLK 16 System block diagram 48 P1.14/HRXD/I0.SDA 47 P1.13/HCLK/I0.SCL 46 P1.10/USBCLK 45 P1.9/PRN.11 44 VSS 43 P1.12/CANTX/USBDN 42 P1.11/CANRX/USBDP 41 P1.8/PPS 40 P1.7/T1.OCMPA 39 VSSIO-PLL ...
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... AV 10/20 Function to guarantee on-chip SS18 to guarantee on-chip SSBKP are all internally connected. Same for pins must be tied together to the common ground plane, taking SSBKP SS SS STA2058 LQFP 64 LFBGA144 D2,A3,K3,F6, E9,B10 4, 8, 44, D1,A2,F4,L4,M 50 F5, D7,E10 38 H12 39 H11 ...
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... STA2058 4 Electrical characteristic 4.1 DC electrical characteristic V = 3.3 V ± Table 4. DC electrical characteristic Symbol Parameter Input high level CMOS V IH Input high level Input low level CMOS V IL Input low level Input hysteresis CMOS Schmitt trigger V HYS Input hysteresis Schmitt trigger Output high level ...
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... Main VReg off, Flash in power-down LP VReg and 32kHz Osc on LP VReg, LVD, 32kHz Osc bypassed = - °C unless otherwise specified. A System clock Executing from RAM or EMI = - °C unless otherwise specified. A System clock STA2058 Value Unit Min. Typ. Max 300 µ ...
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... STA2058 4.4 Flash electrical characteristics = 3.3 ± 10 Table 8. Flash program/erase characteristics 1 Symbol Parameter t Word program PW t Double word program PDW t Bank 0 program (256K) PB0 t Bank 1 program (16K) PB1 t Sector erase (64K Sector erase (8K Bank 0 erase (256K Bank 1 erase (16K Recovery from power-down ...
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... Total harmonic distortion 14/ °C unless otherwise specified. A DEVICE Test conditions Stable 3.3V ± °C unless otherwise specified. VDD A Test conditions Sinewave with ΔV IN amplitude STA2058 DEVICE Value Unit Min Typ Max μA/V 8 2.5 s Value Unit Min Typ Max 12 bits 0 2.5 V 2.1 ...
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... STA2058 Table 11. ADC electrical characteristics (continued) Symbol Parameter Z Input impedance IN C Input capacitance IN I Power consumption ADC I Standby power consumption STBY 4.7 PLL electrical characteristics = 3.3 ± Table 12. PLL electrical characteristics Symbol Parameter T PLL reference clock PLL1 T PLL reference clock PLL2 ...
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... TTFF Warm start Cold start Accuracy Autonomous Acquisition (Warm start) Sensitivity Tracking 16/ °C, unless otherwise specified A Test conditions 50%, -130dBm, Fu 2ppm, Tu ± 30km CEP 50%, 24hr static at - 130dBm With external LNA STA2058 Value Unit Min Typ Max <1 s <2.5 s <34 s < -146 dBm ...
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... STA2058 5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 6. LQFP64 mechanical data and package dimensions DIM. ...
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... Low Profile Fine Pitch Ball Grid Array 0.08 0.0031 OUTLINE AND MECHANICAL DATA Body 1.7mm LFBGA144 7163385 D STA2058 ...
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... STA2058 6 Revision history Table 15. Document revision history Date 23-Apr-2007 25-Jun-2007 19-Mar-2009 Revision 1 Initial release. Added features summary, pin description, electrical characteristics 2 and packages information. Updated Table 1: Device summary on page 3 Updated ECOPACK description in page 17. Revision history Changes 1. Section 5: Package information on 19/20 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 20/20 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA2058 ...