STA1052S1 STMicroelectronics, STA1052S1 Datasheet

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STA1052S1

Manufacturer Part Number
STA1052S1
Description
DSP/MCU SYSTEM 144-LQFP
Manufacturer
STMicroelectronics
Datasheet

Specifications of STA1052S1

Applications
Automotive
Core Processor
ARM7
Program Memory Type
ROM (384 kB)
Ram Size
128K x 8
Interface
I²C, I²S, SPI, UART, USB
Voltage - Supply
1.71 V ~ 1.89 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Controller Series
-

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Features
Embedded ARM7TDMI microcontroller
Analog Front-end part
Digital servo
March 2008
For further information contact your local STMicroelectronics sales office.
CD-R, CD-RW playback
Audio decoding (MP3,WMA,AAC)
CLV (1x, 2x, 4x) and CAV mode (6x)
On-chip USB-OTG host full speed
3.3 V ±5 % operating supply range for I/O
1.8 V ±5 % operating supply range for logic
IDLE, WFI and STOP modes
Power on reset / Brownout controller
33.8688 MHz external quartz/resonator
Operating temperature range: -40 °C to +85 °C
32 bit MCU with 3-stage pipeline @ 67 MHz
384 KB internal ROM (4 Mb on package RAM
for development version) and 128 KB RAM
I
Two high-speed UART full-duplex
Two buffered SPI master/slave interface
A, B, C, D, E, F voltage inputs
Automatic gain and offset control
ALPC circuit with integrated Power MOS
8 bit 2 channels general purpose ADC
Automatic fine gain/balance/offset adjustment
for tracking and focus
Embedded 16 bit servo DSP (33.8688 MHz)
PDM controls for focus, tracking, spindle, sledge
Embedded stepping sledge motor controller
CLV & CAV spindle control
2
C master/slave (400 kHz) + 1 CRQ line
DSP/MCU system for CD-DA, CD-CA, CD-ROM player
Rev 1
Acquisition
Error correction
Shock-proof controller
Audio features
Development environment
Table 1.
Order code
STA1052S1
Full range adjustment-free digital PLL
EFM demodulation and synchronization
Q subcode and CD text decoder
CIRC, capable of dual C1, quad C2 erasure
RSPC capable of C3 corrections
Jitter absorbing capacity ±24 frames (CLV)
Up to 64 Mbit external SDRAM interface
8/16 bit data bus interface
ADPCM (4:1) lossy compression for extended
shock proof capability
Two I
SPDIF transmitter (IEC958) and receiver
Sample-rate conversion from 8 kHz - 48 kHz
input to 44.1 kHz output
Digital equalizer for bass/treble control
Built-in stereo DAC
5 pin JTAG port (IEEE 1149.1 standard)
2
S transmitters and one I
LQFP144 (20x20x1.4 mm)
Device summary
LQFP144
Package
STA1052
2
S receiver
Packing
Tray
Data Brief
www.st.com
1/14
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Related parts for STA1052S1

STA1052S1 Summary of contents

Page 1

... Digital equalizer for bass/treble control ■ Built-in stereo DAC Development environment ■ 5 pin JTAG port (IEEE 1149.1 standard) Table 1. Device summary Order code Package STA1052S1 LQFP144 Rev 1 STA1052 Data Brief 2 S receiver Packing Tray 1/14 www.st.com 14 ...

Page 2

Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

STA1052 1 Description The STA1052 is a single chip device which performs all functions related to read back of optical disk: servo control operations, reading optical disc decoding the High frequency signals, EFM decoding, error correction, software decoding of MP3 ...

Page 4

System block diagram 2 System block diagram Figure 1 provides the complete system block diagram, where the ARM sub-system is represented as a hierarchical block. Figure 1. STA1052 block diagram Output interface SPDIF-SONYLSI-I2S 4/14 master clock ARM Subsystem ADPCM Decoder ...

Page 5

STA1052 3 Pin description 3.1 Pin connection Figure 2. LQFP144 pin configuration (top view) 144 143 142 DRD9 1 2 DRD8 3 GPB12 4 GPB13 GPB14 5 6 GPB15 7 DRD7 8 DRD6 9 DRD5 VDD 10 VSS 11 12 ...

Page 6

Pin description 3.2 Pin function description This pin list contains the definition and description of all pins. Table 2 gives pin list for LQFP144. Table 2. Pin List N° Name 1 GPC9(DRD9) 2 GPC8(DRD8) 3 GPB12 4 GPB13 5 GPB14 ...

Page 7

STA1052 Table 2. Pin List (continued) N° Name 27 FE_B 28 FE_D 29 FE_E 30 FE_F 31 FE_VDDA33S 32 FE_VDDPAD1 33 FE_ADCIN1 34 FE_ADCIN2 35 FE_VREF_ADC 36 FE_VREF 37 FE_VDDA33R 38 FE_CEXT 39 FE_REXT 40 FE_VSSA33R 41 FE_MD_LAS 42 FE_CAP_LAS ...

Page 8

Pin description Table 2. Pin List (continued) N° Name 57 SPDL 58 SLED1 59 SLED2 60 VDD 61 VSS 62 VDD3 63 TFSR 64 CAV 65 LRCK 66 GPA9 67 GPA10 68 GPA11 69 GPA12 70 SDO/SPDIF 71 BCLK 72 ...

Page 9

STA1052 Table 2. Pin List (continued) N° Name 79 GPA6 (EINT6) 80 GPA7 (EINT7) 81 GPA8 (EINT8) GPB0/SFLASH_SS 82 (EINT9) 83 VSS 84 VDD3_Core2 GPB1/I2C_CRQ 85 (EINT10) GPB2/I2C_SCL 86 (EINT11) GPB3/I2C_SDA 87 (EINT12) 88 GPB4/SCI0TX GPB5/SCI0RX 89 (EINT13) 90 GPB8/C2PO/USBCK ...

Page 10

Pin description Table 2. Pin List (continued) N° Name 103 VCM 104 ADAC_REF1 105 OUTR - NC 106 JTCK 107 JTRST 108 DRBA1 109 DRBA0/CFG4 110 DRA11/CFG3 111 DRA10/CFG2 112 DRA9/CFG1 113 DRA8/CFG0 114 DRA7 115 DRA6 116 DRA5 117 ...

Page 11

STA1052 Table 2. Pin List (continued) N° Name 130 VSS 131 VDD3_Core1 132 GPC15 (DRD15) 133 GPC14 (DRD14) 134 GPC13 (DRD13) 135 GPC12 (DRD12) 136 GPB9 137 GPB10 138 GPB11 139 GPC11 (DRD11) 140 GPC10 (DRD10) 1. The specifications in ...

Page 12

Package information 4 Package information In order to meet environmental requirements, ST (also) offers these devices in ECOPACK packages. ECOPACK is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings ...

Page 13

STA1052 5 Revision history Table 3. Document revision history Date 12-Mar-2008 Revision 1 Initial release. Revision history Changes 13/14 ...

Page 14

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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