AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 52

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

Members of the EZ-USB family that provide pins to expand 8051 memory provide sepa-
rate non-multiplexed 16-bit address and 8-bit data busses. This differs from the standard
8051, which multiplexes eight device pins between three sources: IO port 0, the external
data bus, and the low byte of the address bus. A standard 8051 system with external mem-
ory requires a de-multiplexing address latch, strobed by the 8051 ALE (Address Latch
Enable) pin. The external latch is not required by the non-multiplexed EZ-USB chip, and
no ALE signal is needed. In addition to eliminating the customary external latch, the non-
multiplexed bus saves one cycle per memory fetch cycle, further improving 8051 perfor-
mance.
A standard 8051 user must choose between using Port 0 as a memory expansion port or an
IO port. The AN2131Q provides a separate IO system with its own control registers (in
external memory space), and provides the IO port signals on dedicated (not shared) pins.
This allows the external data bus to be used to expand memory without sacrificing IO
pins.
The 8051 is the sole master of the memory expansion bus. It provides read and write sig-
nals to external memory. The address bus is output-only.
A special fast transfer mode gives the EZ-USB family the capability to transfer data to
and from external memory over the expansion bus using a single MOVX instruction,
which takes only two cycles (eight clocks) per byte.
The internal 8051 RESET signal is not directly controlled by the EZ-USB RESET pin.
Instead, it is controlled by an EZ-USB register bit accessible to the USB host. When the
EZ-USB chip is powered, the 8051 is held in reset. Using the default USB device (enu-
merated by the USB core), the host downloads code into RAM. Finally, the host clears an
EZ-USB register bit that takes the 8051 out of reset.
The EZ-USB family also operates with external non-volatile memory, in which case the
8051 exits the reset state automatically at power-on. The various EZ-USB resets and their
effects are described in Chapter 10, "EZ-USB Resets."
EZ-USB TRM v1.9
2.10
2.11
Internal Bus
Reset
Chapter 2. EZ-USB CPU
Page 2-7