CY7C63613-SC Cypress Semiconductor Corp, CY7C63613-SC Datasheet
CY7C63613-SC
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... CY7C63612/13 Low-Speed, Low I/O 1.5 Mbps USB Controller Cypress Semiconductor Corporation PRELIMINARY • 3901 North First Street • San Jose CY7C63612/13 • CA 95134 • 408-943-2600 March 26, 1999 ...
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FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 3.0 PIN ASSIGNMENTS ....................................................................................................................... 8 4.0 PROGRAMMING MODEL ............................................................................................................... 8 4.1 14-bit Program Counter (PC) ........................................................................................................... 8 4.2 8-bit Accumulator (A) ....................................................................................................................... 8 4.3 8-bit Index Register (X) .................................................................................................................... 8 4.4 ...
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USB Endpoint Interrupts ..................................................................................................................... 23 14.2.4 DAC Interrupt ...................................................................................................................................... 23 14.2.5 GPIO Interrupt .................................................................................................................................... 23 15.0 TRUTH TABLES .........................................................................................................................23 16.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 26 17.0 DC CHARACTERISTICS ............................................................................................................ 27 18.0 SWITCHING CHARACTERISTICS ............................................................................................. 28 19.0 ORDERING INFORMATION .......................................................................................................30 ...
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Figure 6-1. Program Memory Space with Interrupt Vector Table ......................................................... 11 Figure 7-1. Clock Oscillator On-chip Circuit .......................................................................................... 14 Figure 8-1. Watch Dog Reset (WDR) ................................................................................................... 15 Figure 9-1. Block Diagram of a GPIO Line ........................................................................................... 15 Figure 9-2. Port ...
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... CPU clock • Internal memory — 256 bytes of RAM — 6 Kbytes of EPROM (CY7C63612) — 8 Kbytes of EPROM (CY7C63613) • Interface can auto-configure to operate as PS2 or USB • I/O port — 12 General-Purpose I/O (GPIO) pins (Port capable of sinking 7 mA per pin (typical) — ...
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... The CY7C63612/13 are offered with two EPROM options to maximize flexibility and minimize cost. The CY7C63612 has 6 Kbytes of EPROM. The CY7C63613 has 8 Kbytes of EPROM. These parts include power-on reset logic, a watch dog timer, a vectored interrupt controller, and a 12-bit free-running timer. The Power-On Reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h ...
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Logic Block Diagram 6-MHz ceramic resonator OSC 12 MHz 6 MHz 12-MHz USB 8-bit Transceiver CPU USB EPROM 4/6/8 Kbyte RAM Interrupt 256 byte Controller 12-bit GPIO Timer PORT 0 GPIO PORT 1 GPIO PORT 2 Watch Dog Timer ...
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... Pin Assignments CY7C63613 Name I/O 24-Pin D+, D– I/O 1,2 P0[7:0] 7,18,8,17, I/O 9,16,10,15 P1[3:0] 5,20,6,19 I/O P2 n/a I/O P3[7:4] 3,22,4,21 I/O DAC I/O n/a XTAL XTAL OUT 14 OUT Vss 12,23 4.0 Programming Model 4.1 14-bit Program Counter (PC) The 14-bit Program Counter (PC) allows access for kilobytes of EPROM using the CY7C636xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h ...
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The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack ...
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Instruction Set Summary MNEMONIC operand HALT ADD A,expr data ADD A,[expr] direct ADD A,[X+expr] index ADC A,expr data ADC A,[expr] direct ADC A,[X+expr] index SUB A,expr data SUB A,[expr] direct SUB A,[X+expr] index SBB A,expr data SBB A,[expr] direct ...
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... USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here 0x0FFF 0x17FF 6-KB PROM ends here (CY7C63612) ( bytes) 0x1FDF 8-KB PROM ends here (CY7C63613) 11 CY7C63612/13 ...
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Data Memory Organization The CY7C63612/13 microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: after reset 8-bit PSP ...
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I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write ...
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Clocking Clock Distribution clk1x (to USB SIE) clk2x (to Microcontroller) The XTAL and XTAL are the clock pins to the microcontroller. The user can connect a low-cost ceramic resonator OUT external oscillator can be connected to ...
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Watch Dog Reset (WDR) The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal reset initialization noted under “Reset,” ...
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GPIO port is configured for CMOS outputs and the output data bit is written as a “1”. Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of current to ...
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GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In ad- dition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising ...
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USB Enumeration The enumeration sequence is shown below: 1. The host computer sends a Setup packet followed by a Data packet to USB address 0 requesting the Device descriptor. 2. The USB Controller decodes the request and retrieves its ...
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Control Bits 000 001 010 011 100 101 110 111 11.0 USB Device USB Device Address A includes three endpoints: EPA0, EPA1, and EPA2. End Point 0 (EPA0) allows the USB host to recognize, set up, and control the device. ...
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The ‘set-up’ PID status (bit[7]) is forced HIGH from the start of the data packet phase of the set-up transaction, until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during ...
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Processor Status and Control Register R/W IRQ Watch Dog USB Bus Pending Reset Figure 13-1. Processor Status and Control Register 0xFFh The “Run” (bit 0) is manipulated by the HALT instruction. When Halt is executed, the ...
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Reserved Reserved Reserved Figure 14-2. USB End Point Interrupt Enable Register 0x21h (read/write) Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the hardware will first disable all interrupts ...
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Timer Interrupt There are two timer interrupts: the 128- s interrupt and the 1.024-ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the interrupts first or the ...
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The ‘In’ column represents the SIE’s response to the token type. A disabled endpoint will remain such until firmware changes it, and all endpoints reset to disabled. Any Setup packet to an enabled and accepting endpoint will be changed by ...
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Table 15-3. Details of Modes for Differing Traffic Conditions End Point Mode token count buffer Setup Packet (if accepting) See Table 15-1 Setup <= 10 data See Table 15-1 Setup > 10 junk See Table 15-1 ...
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Table 15-3. Details of Modes for Differing Traffic Conditions (continued Out Out != Out > Out ...
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DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C Parameter General V Operating Voltage CC (1) V Operating Voltage CC ( Operating Supply Current CC1 4.35V CC2 CC I Supply ...
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Switching Characteristics Parameter Description Clock t Input Clock Cycle Time CYC t Clock HIGH Time CH t Clock LOW Time CL USB Driver Characteristics t Transition Rise Time r t Transition Rise Time r t Transition Fall Time f ...
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FOR PRELIMINARY crs 10 Figure 18-2. USB Data Signal Timing T PERIOD Differential Data Lines Figure 18-3. Receiver Jitter Tolerance T PERIOD Crossover Point Differential Data Lines ...
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... Ordering Information EPROM Ordering Code Size CY7C63612- CY7C63613- Document #: 38-00754 20.0 Package Diagram © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...