CY7C63221A-PXC Cypress Semiconductor Corp, CY7C63221A-PXC Datasheet - Page 27

• Manufacturer Part Number: CY7C63221A-PXC
• Description: IC MCU 3K USB LS PERIPH 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63221A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1861; CY7C63221A-PXC

Bit [3:0]: Mode Bit [3:0]
14.4
There are two Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in Figure 14-4.
Bit 7: Data Toggle
Bit 6: Data Valid
Bit [5:4]: Reserved
Bit [3:0]: Byte Count Bit [3:0]
15.0
The VREG pin provides a regulated output for connecting the pull-up resistor required for USB operation. For USB, a 1.5-kΩ
resistor is connected between the D– pin and the VREG voltage, to indicate low-speed USB operation. Since the VREG output
has an internal series resistance of approximately 200Ω, the external pull-up resistor required is R
The regulator output is placed in a high-impedance state at reset, and must be enabled by firmware by setting the VREG Enable
bit in the USB Status and Control Register (Figure 13-1). This simplifies the design of a combination PS/2-USB device, since the
USB pull-up resistor can be left in place during PS/2 operation without loading the PS/2 line. In this mode, the VREG pin can be
used as an input and its state can be read at port P2.0. Refer to Figure 12-8 for the Port 2 data register. This input has a TTL
threshold.
In suspend mode, the regulator is automatically disabled. If VREG Enable bit is set (Figure 13-1), the VREG pin is pulled up to
V
Note that enabling the device for USB (by setting the Device Address Enable bit, Figure 14-1) activates the internal regulator,
even if the VREG Enable bit is cleared to 0. This insures proper USB signaling in the case where the VREG pin is used as an
input, and an external regulator is provided for the USB pull-up resistor. This also limits the swing on the D– and D+ pins to about
1V above the internal regulator voltage, so the Device Address Enable bit normally should only be set for USB operating modes.
The regulator output is only designed to provide current for the USB pull-up resistor. In addition, the output voltage at the VREG
pin is effectively disconnected when the device transmits USB from the internal SIE. This means that the VREG pin does not
provide a stable voltage during transmits, although this does not affect USB signaling.
Document #: 38-08028 Rev. *B
Read/Write
CC
Bit Name
The EP1 Mode Bits operate in the same manner as the EP0 Mode Bits (see Section 14.2).
This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to the select the transmitted
Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
1 = DATA1
0 = DATA0
This bit is used for OUT and SETUP tokens only. This bit is cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred. This
bit does not update for some endpoint mode settings. Refer to Table 20-3 for more details.
1 = Data is valid.
0 = Data is invalid. If enabled, the endpoint interrupt will occur even if invalid data is received.
Byte Count Bits indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with the
number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP
transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values
are 2 to 10 inclusive.
For Endpoint 0 Count Register, whenever the count updates from a SETUP or OUT transaction, the count register locks and
cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on
incoming SETUP or OUT transactions before firmware has a chance to read the data.
Reset
Bit #
with an internal 6.2-kΩ resistor. This holds the proper V
USB Endpoint Counter Registers
USB Regulator Output
Data Toggle
R/W
7
0
Figure 14-4. Endpoint 0 and 1 Counter Registers (Addresses 0x11 and 0x13)
Data Valid
R/W
6
0
FOR
FOR
5
0
-
Reserved
OH
4
0
-
state in suspend mode.
R/W
3
0
R/W
2
0
Byte Count
CY7C63221/31A
enCoRe™ USB
PU
(see Section 23.0).
R/W
1
0
Page 27 of 50
R/W
0
0
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