CY7C64013C-PXC Cypress Semiconductor Corp, CY7C64013C-PXC Datasheet - Page 16

• Manufacturer Part Number: CY7C64013C-PXC
• Description: IC MCU 8K FULL SPEED USB 28DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-PXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1846

Table 5. Port 1 Data
Table 6. Port 2 Data
Table 7. Port 3 Data
Special care should be taken with any unused GPIO data bits.
An unused GPIO data bit, either a pin on the chip or a port bit
that is not bonded on a particular package, must not be left
floating when the device enters the suspend state. If a GPIO data
bit is left floating, the leakage current caused by the floating bit
may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the
port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port
bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C64013C part always requires that the
data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’
In normal non-HAPI mode, reads from a GPIO port always return
the present state of the voltage at the pin, independent of the
settings in the Port Data Registers. If HAPI mode is activated for
Table 8. GPIO Configuration Register
As shown in
input pin represents a rising edge interrupt (LOW to HIGH), and
a negative polarity on an input pin represents a falling edge
interrupt (HIGH to LOW).
The GPIO interrupt is generated when all of the following
conditions are met: the Interrupt Enable bit of the associated Port
Document Number: 38-08001 Rev. *D
Port 1 Data
Bit #
Bit Name
Read/Write
Reset
Port 2 Data
Bit #
Bit Name
Read/Write
Reset
Port 3 Data
Bit #
Bit Name
Read/Write
Reset
GPIO
Configuration
Bit #
Bit Name
Read/Write
Reset
Table 9 on page 17
Config Bit 1
Port 3
P1.7
P2.7
P3.7
R/W
R/W
R/W
R/W
7
1
7
1
7
1
7
0
Config Bit 0
below, a positive polarity on an
Port 3
P3.6
P1.6
R/W
P2.6
R/W
R/W
R/W
6
1
6
1
6
1
6
0
Config Bit 1
Port 2
P1.5
P2.5
P3.5
R/W
R/W
R/W
R/W
5
1
5
1
5
1
5
0
Config Bit 0
Port 2
P1.4
P2.4
P3.4
R/W
R/W
R/W
R/W
4
1
4
1
4
1
4
0
a port, reads of that port return latched data as controlled by the
HAPI signals (see
on page
high-impedance input state (‘1’ in open drain mode). Writing a ‘0’
to a GPIO pin drives the pin LOW. In this state, a ‘0’ is always
read on that GPIO pin unless an external source overdrives the
internal pull-down device.
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal
pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not
driven internally). In addition, the interrupt polarity for each port
can be programmed. The Port Configuration bits
the Interrupt Enable bit
on page
Interrupt Enable Register is enabled, the GPIO Interrupt Enable
bit of the Global Interrupt Enable Register
is enabled, the Interrupt Enable Sense (bit 2,
Table 27 on page
an event matching the interrupt polarity.
Config Bit 1
Port 1
P1.3
P2.3
P3.3
R/W
R/W
R/W
R/W
18) determine the interrupt polarity of the port pins.
3
1
3
1
3
1
24). During reset, all of the GPIO pins are set to a
3
0
25) is set, and the GPIO pin of the port sees
Hardware Assisted Parallel Interface (HAPI)
Config Bit 0
Port 1
P1.2
P2.2
R/W
R/W
R/W
R/W
P32
2
1
2
1
2
1
2
0
(Table 10 on page 17
Config Bit 1
Port 0
P1.1
P2.1
P3.1
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
0
CY7C64013C
CY7C64113C
(Table 28 on page
ADDRESS 0x03
ADDRESS 0x01
ADDRESS 0x02
ADDRESS 0x08
through
Config Bit 0
Page 16 of 53
(Table
Port 0
P1.0
P2.0
P3.0
R/W
R/W
R/W
R/W
0
1
0
1
0
1
0
0
Table 13
8) and
26)
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