CY7C64714-56LFXC Cypress Semiconductor Corp, CY7C64714-56LFXC Datasheet - Page 5

• Manufacturer Part Number: CY7C64714-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64714-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Table 4-4. Individual FIFO/GPIF Interrupt Sources
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX1 substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically-inserted INT4VEC byte at
0x0055 will direct the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack then jumps to
address 0x0053, where it expects to find a “jump” instruction
to the ISR Interrupt service routine.
4.9
4.9.1
The input pin, RESET#, will reset the FX1 when asserted. This
pin has hysteresis and is active LOW. When a crystal is used
with the CY7C64713/4 the reset period must allow for the
Document #: 38-08039 Rev. *C
3.
Priority
RESET#
If the external clock is powered at the same time as the CY7C64713/4 and has a stabilization wait period, it must be added to the 200 s.
VCC
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Reset and Wakeup
Reset Pin
INT4VEC Value
AC
8C
9C
80
88
90
94
98
A0
A4
T
A8
B0
B4
84
Power on Reset
RESET
GPIFDONE
GPIFWF
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
Figure 4-2. Reset Timing Plots
3.3V
V
3.0V
0V
IL
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
RESET#
stabilization of the crystal and the PLL. This reset period
should be approximately 5 ms after VCC has reached 3.0
Volts. If the crystal input pin is driven by a clock signal the
internal PLL stabilizes in 200
3.0V
reset applied during operation. A power on reset is defined as
the time reset is asserted while power is being applied to the
circuit. A powered reset is defined to be when the FX1 has
previously been powered on and operating and the RESET#
pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cypress web site. While the application note discusses
the FX2, the information provided applies also to the FX1. For
more information on reset implementation for the FX2 family
of products visit the http://www.cypress.com.
VCC
[3]
. Figure 4-2 shows a power on reset condition and a
T
RESET
Notes
Powered Reset
s after VCC has reached
CY7C64713/14
V
3.3V
0V
IL
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