EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 42

• Manufacturer Part Number: EZ80L92AZ020SG
• Description: IC WEBSERVER 20MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3876; EZ80L92AZ020SG

PS013014-0107
Table 4. Clock Peripheral Power-Down Register 1 (CLK_PPD1 = 00DBh)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit Position
7
GPIO_D_OFF
6
GPIO_C_OFF
5
GPIO_B_OFF
4
3
SPI_OFF
2
I2C_OFF
1
UART1_OFF
0
UART0_OFF
Value
R/W
1
0
1
0
1
0
1
0
1
0
1
0
1
0
7
0
Description
System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
System clock to GPIO Port D is powered up.
System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
System clock to GPIO Port C is powered up.
System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
System clock to GPIO Port B is powered up.
Reserved.
System clock to SPI is powered down.
System clock to SPI is powered up.
System clock to I
System clock to I
System clock to UART1 is powered down.
System clock to UART1 is powered up.
System clock to UART0 and IrDA endec is powered down.
System clock to UART0 and IrDA endec is powered up.
R/W
6
0
R/W
5
0
2
2
C is powered down.
C is powered up.
R
4
0
R/W
3
0
Product Specification
R/W
2
0
Low-Power Modes
R/W
1
0
R/W
0
0
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