MPC859TVR133A Freescale Semiconductor, MPC859TVR133A Datasheet - Page 71

• Manufacturer Part Number: MPC859TVR133A
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC859TVR133A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 28
Table 29
Freescale Semiconductor
1
1
Num
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
200
200
202
203
204
205
206
207
208
209
210
211
Num
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
200
200
202
203
204
205
206
207
208
209
210
211
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
shows the I
shows the I
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
2
2
C (SCL < 100 kHz) timings.
C (SCL > 100 kHz) timings.
Characteristic
MPC866/MPC859 Hardware Specifications, Rev. 2
Characteristic
Table 29. I
Table 28. I
1
1
2
2
C Timing (SCL < 100 kHz)
C Timing (SCL > 100 kHz)
Expression
fSCL
fSCL
—
—
—
—
—
—
—
—
—
—
BRGCLK/16512
1/2(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(40 * fSCL)
Min
—
—
0
0
All Frequencies
Min
250
All Frequencies
1.5
4.7
4.7
4.0
4.7
4.0
4.7
—
—
0
0
CPM Electrical Characteristics
1/(10 * fSCL)
1/(33 * fSCL)
BRGCLK/48
BRGCLK/48
Max
Max
100
100
300
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
Unit
kHz
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
Unit
Hz
Hz
s
s
s
s
s
s
s
s
s
s
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