MPC8541EVTAPF Freescale Semiconductor, MPC8541EVTAPF Datasheet - Page 17

• Manufacturer Part Number: MPC8541EVTAPF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8541EVTAPF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 833MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 1.14V To 1.26V
• Rohs Compliant: Yes
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

At recommended operating conditions with GV
6.2
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
Table 13
6.2.2
Table 14
DDR SDRAM interface.
Freescale Semiconductor
At recommended operating conditions with GV
AC input low voltage
AC input high voltage
MDQS—MDQ/MECC input skew per
byte
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS(n) output setup with respect to MCK
7) or ECC (MECC[{0...7}] if n = 8).
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the input AC timing specifications for the DDR SDRAM interface.
and
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
DDR SDRAM AC Electrical Characteristics
DDR SDRAM Input AC Timing Specifications
DDR SDRAM Output AC Timing Specifications
Parameter
Table 15
For DDR = 333 MHz
For DDR < 266 MHz
Parameter
provide the output AC timing specifications and measurement conditions for the
Table 13. DDR SDRAM Input AC Timing Specifications
DD
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DD
of 2.5 V ± 5%.
of 2.5 V ± 5%.
Symbol
t
DISKEW
V
V
IH
IL
Symbol
t
t
t
t
AOSKEW
DDKHAS
DDKHAX
DDKHCS
t
MCK
MV
1
REF
Min
—
—
+ 0.31
–1000
–1100
–1200
3.45
2.65
3.45
Min
2.8
4.6
2.0
3.8
2.8
4.6
6
MV
GV
REF
DD
1125
Max
750
– 0.31
+ 0.3
Max
200
300
400
10
—
—
—
Unit
ps
V
V
Unit
ns
ps
ns
ns
ns
DDR SDRAM
Notes
Notes
—
—
1
2
3
4
4
4
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