MPC8241LVR166D Freescale Semiconductor, MPC8241LVR166D Datasheet - Page 44

• Manufacturer Part Number: MPC8241LVR166D
• Description: IC MPU 32BIT 166MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8241LVR166D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 166MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xxx
• Core: 603e
• Maximum Clock Frequency: 166 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Design Information
7.4
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and
PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]
and PAR[4:7]) are disabled, and their outputs drive logic zeros when they would otherwise be driven. For
this mode, these pins do not require pull-up resistors and should be left unconnected to minimize possible
output switching.
The TEST0 pin requires a pull-up resistor of 120 Ω or less connected to GV
RTC should have weak pull-up resistors (2–10 kΩ) connected to GV
signals should be pulled up to GV
SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, QACK/DA0, and
DRDY.
The following PCI control signals should be pulled up to LV
resistors (2–10 kΩ): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor
values may need to have stronger adjustment to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See
The following pins have internal pull-up resistors that are enabled only while the device is in the reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], and PMAA[0:2]. See
Table
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset configuration pins should be tied to GND by means of 1-kΩ pull-down resistors to ensure that a logic
zero level is read into the configuration bits during reset if the default logic-one level is not desired.
Any other unused active low input pins should be tied to a logic-one level by means of weak pull-up
resistors (2–10 kΩ) to the appropriate power supply listed in
should be tied to GND by means of weak pull-down resistors (2–10 kΩ).
7.5
The MPC8241 PCI reference voltage (LV
interfacing the MPC8241 into a 3.3-V PCI bus system. Similarly, the LV
5.0 V ± 5% power supply if interfacing the MPC8241 into a 5-V PCI bus system. For either reference
voltage, the MPC8241 always performs 3.3-V signaling as described in the PCI Local Bus Specification
(Rev. 2.2). The MPC8241 tolerates 5-V signals when interfaced into a 5-V PCI bus system. (See Errata
No. 18 in the MPC8245/MPC8241 Integrated Processor Chip Errata)
44
16.
Pull-Up/Pull-Down Resistor Requirements
PCI Reference Voltage—LV
Table
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
16.
DD
_OV
DD
DD
) pins should be connected to 3.3 ± 0.3 V power supply if
with weak pull-up resistors (2–10 kΩ): SDA, SCL, SMI,
DD
DD
Table
(the clamping voltage) with weak pull-up
16. Unused active high input pins
DD
.
_OV
DD
DD
pins should be connected to
DD
_OV
and that the following
DD
Freescale Semiconductor
.