MPC8347VRADDB Freescale Semiconductor, MPC8347VRADDB Datasheet - Page 29

• Manufacturer Part Number: MPC8347VRADDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347VRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 14
8.2.4
Table 27
Freescale Semiconductor
At recommended operating conditions with LV
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock cycle duration
Duty cycle for 1000Base-T
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
Fall time (20%–80%)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For
2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
3. For 10 and 100 Mbps, t
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long
5. Duty cycle reference is LV
6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention.
example, the subscript of t
follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).
to the associated clock signal.
as the minimum duty cycle is not violated and stretching occurs for no more than three t
presents the RGMII and RTBI AC timing specifications.
shows the TBI receive AC timing diagram.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
RGMII and RTBI AC Timing
PMA_RX_CLK1
PMA_RX_CLK0
Parameter/Condition
3
RCG[9:0]
RGT
4, 5
DD
RGT
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
/2.
Table 27. RGMII and RTBI AC Timing Specifications
represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times
2
Figure 14. TBI Receive AC Timing Diagram
DD
t
t
SKTRX
TRXH
t
of 2.5 V ± 5%.
TRDVKH
3, 5
t
TRX
t
TRXH
Even RCG
Specifications
t
t
t
G125H
RGTH
RGTH
Symbol
t
t
t
SKRGT
SKRGT
t
t
t
RGTR
RGTF
G12
t
RGT
TRXF
/t
/t
/t
6
RGT
RGT
G125
1
Odd RCG
t
TRDXKH
Ethernet: Three-Speed Ethernet, MII Management
t
–0.5
TRXR
Min
1.0
7.2
45
40
47
—
—
—
t
TRDVKH
RGT
t
TRDXKH
of the lowest speed transitioned.
Typ
8.0
8.0
50
50
—
—
—
—
—
Max
0.75
0.75
0.5
2.8
8.8
55
60
53
—
Unit
ns
ns
ns
ns
ns
ns
%
%
%
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