Z8018010VSG Zilog, Z8018010VSG Datasheet - Page 22

• Manufacturer Part Number: Z8018010VSG
• Description: IC 10MHZ Z180 CMOS MPU 68-PLCC
• Manufacturer: Zilog

Specifications of Z8018010VSG

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

PS014004-1106
A
0
–A
18
MREQ
D
(A
0
On the Z80180, this choice makes the processor fetch a
when fetching a
are not fully Z80-timing compatible but are compatible with the on-chip CTCs.
When
fetching a
refetches the instruction using fully Z80-compatible cycles that include driving
Some external Z80 peripherals may require properly decoded
illustrates the
M1TE (M1 Temporary Enable)—
assertion of the
When
device(s) may require a pulse on M1 after programming certain of their registers to complete
the function being programmed.
For example, when a control word is written to the Z80
actually takes place until the
change in the operation of the
signal and
next opcode fetch cycle regardless of the state
programmed into the
not required to preprogram a
–D
RD
M1
ST
19
φ
7
)
T
M1E = 0
M1E
1
RETI
T
M1E
Figure 9. RETI Instruction Sequence with MIE = 0
2
is set to
PC
RETI
EDh
, the processor does not drive
T
M1
controls its function. When
instruction one time only, with normal timing, the processor goes back and
3
RETI
sequence when
T
signal. It is always read back as a
0
1
M1E
to accommodate certain external Z80 peripheral(s), those same
from zero-wait-state memory uses three clock machine cycles, which
T
2
bit. This instance is only momentary (one time only) and you are
4Dh
T
PIO
1
3
M1
to disable the function (see
PC+1
T
identifies an active
This bit controls the temporary
I
M1E = 0
T
I
T
I
.
M1TE = 0
M1
T
1
Low during instruction fetch cycles. After
T
2
M1
, the
1
EDh
and is set to
T
PC
RETI
PIO
3
signal. When
M1
Figure
T
to enable interrupts, no enable
I
instruction one time only, and
RETI
output is asserted during the
T
1
10).
instructions.
Microprocessor Unit
1
T
during
2
M1TE = 1
PC+1
4Dh
T
3
RESET
T
I
M1
, there is no
Architecture
Figure 9
Low.
Z80180
.
16