Z8L18020PSG Zilog, Z8L18020PSG Datasheet - Page 23

• Manufacturer Part Number: Z8L18020PSG
• Description: IC 20MHZ LOW POWER S180 64-DIP
• Manufacturer: Zilog

Specifications of Z8L18020PSG

• Processor Type: Z80
• Features: Enhanced DMA Support
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8L18x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ZiLOG
Software can put the Z8S180/Z8L180 into this mode by set-
ting the
the
and thus draws the least power of any mode, less than 10µA.
As with
mode in response to a Low on
on
in the INT/TRAP Control Register. This action grants the
bus to an external Master if the BREXT bit in the CPU Con-
trol Register (CCR5) is
operations is greatly increased by the necessity for restart-
ing the on-chip oscillator, and ensuring that it stabilizes to
square-wave operation.
When an external clock is connected to the EXTAL pin rath-
er than a crystal to the XTAL and EXTAL pins and the ex-
ternal clock runs continuously, there is little necessity to use
oscillator, and other modes restart faster. However, if ex-
ternal logic stops the clock during
ample, by decoding
clock cycles), then
the external clock source to stabilize after it is re-enabled.
instruction. This mode stops the on-chip oscillator
–2 that is enabled by a
mode because no time is required to restart the
mode, the Z8S180/Z8L180 leaves
bit (ICR5) to
1
. The time required for all of these
Low and
1
mode can be useful to allow
, CCR6 to
1
in the corresponding bit
, on
High for several
1
, and executing
mode (for ex-
, or a Low
When external logic drives
out of
clock source is stopped, the external logic must hold
Low until the on-chip oscillator or external clock source is
restarted and stabilized.
The clock-stability requirements of the Z8S180/Z8L180 are
much less in the divide-by-two mode that is selected by a
the CPU Control Register (CCR7). As a result, software per-
forms the following actions:
1. Sets CCR7 to
2. Delays setting CCR7 back to
If CCR6 is set to
MPU in
mines the length of the delay before the oscillator restarts
and stabilizes when it leaves
t e r n a l i n t e r r u p t r e q u e s t . W h e n C C R 3 is
Z8S180/Z8L180 waits 2
CCR3 is
instruction and
mode as long as possible to allow additional clock
stabilization time after a
RESTART after an
sequence and controlled by the Clock Divide bit in
1
, it waits 64 clock cycles. This state is called
mode, and a crystal is in use or an external
0
1
mode, the value of the CCR3 bit deter-
for divide-by-two mode before an
mode. The same delay applies to grant-
before the
17
(131,072) clock cycles. When
01 instruction.
mode.
Low to bring the device
1
instruction places the
, interrupt, or in-line
mode due to an ex-
for divide-by-one
0
, t h e