IDT79RC32K438-266BB IDT, Integrated Device Technology Inc, IDT79RC32K438-266BB Datasheet - Page 20

• Manufacturer Part Number: IDT79RC32K438-266BB
• Description: IC MPU 32BIT CORE 266MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-266BB

• Processor Type: MIPS32 32-Bit
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32K438-266BB

AC Timing Characteristics
Reset
COLDRSTN
RSTN
RSTN
MDATA[15:0]
(boot vector)
IDT 79RC32438
Values given below are based on systems running at recommended operating temperatures and supply voltages, shown in Tables 15 and 16.
1.
2.
3.
The COLDRSTN minimum pulse width is the oscillator stabilization time (OSC) plus 0.5 ms with V
The values for this symbol were determined by calculation, not by testing.
RSTN is a bidirectional signal. It is treated as an asynchronous input.
Signal
3
3
(input)
(output)
MDATA[15:0]
COLDRSTN
1
1.
2.
3.
4.
5.
6.
EXTCLK
BDIRN
RSTN
BOEN
CLK
COLDRSTN asserted by external logic. The RC32438 asserts RSTN, asserts BOEN low, drives BDIRN low, disables EXTCLK, and tri-states the data
bus and all output pins in response.
External logic begins driving valid boot configuration vector on the data bus, and the RC32438 starts sampling it.
External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated
before COLDRSTN is negated. The RC32438 stops sampling the boot configuration vector.
The RC32438 starts driving the data bus, MDATA[15:0], negates BOEN, drives BDIRN high, and starts driving EXTCLK.
RSTN negated by the RC32438.
CPU begins executing by taking MIPS reset exception, and the RC32438 starts sampling RSTN as a warm reset input.
Symbol
Tpw_6a
Trise_6a none
Tpw_6b
Tdz_6d
Tdz_6d
Tzd_6d
Thld_6d
Tdo_6c
1
2
2
2
2
2
Tdz_6d
none
none
COLDRSTN
falling
COLDRSTN
rising
COLDRSTN
falling
RSTN falling
RSTN rising
Reference
Edge
2
BOOT VECT
Tpw_6a
OSC +
2(CLK)
2(CLK)
Min
Table 6 Reset and System AC Timing Characteristics
200MHz
0.5
3.0
—
—
—
—
Figure 4 Cold Reset AC Timing Waveform
5(CLK)
Max
15.0
30.0
3
5.0
—
—
—
—
<= 16 CLK
clock cycles
Thld_6d
OSC +
2(CLK)
2(CLK)
Trise_6a
233MHz
Min
0.5
3.0
—
—
—
—
4
20 of 59
>= 4096 CLK clock cycles
5(CLK)
Max
15.0
30.0
5.0
—
—
—
—
OSC +
2(CLK)
2(CLK)
266MHz
Min
0.5
3.0
—
—
—
—
cc
5(CLK)
Max
15.0
30.0
stable.
5.0
—
—
—
—
FFFF_FFFF
5
>= 4096 CLK clock cycles
OSC +
2(CLK)
2(CLK)
300MHz
Min
0.5
3.0
—
—
—
—
5(CLK)
Max
15.0
30.0
5.0
—
—
—
—
Unit
ms
ns
ns
ns
ns
ns
ns
ns
Cold reset
Cold reset
Warm reset
Cold reset
Cold reset
Cold reset
Warm reset
Warm reset
Conditions
6
See Figures 4
and 5.
May 25, 2004
Reference
Diagram
Timing