IDT79R4650-133DP IDT, Integrated Device Technology Inc, IDT79R4650-133DP Datasheet - Page 4

• Manufacturer Part Number: IDT79R4650-133DP
• Description: IC MPU 64BIT W/DSP 133MHZ 208QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R4650-133DP

• Processor Type: RISC 64-Bit
• Speed: 133MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R4650-133DP

the RC4650 will signal a trap when a double-precision operation is initi-
ated, allowing the requested function to be emulated in software. Alter-
natively, the system architect could use a software library emulation of
double-precision functions, selected at compile time, to eliminate the
overhead associated with trap and emulation.
Floating-Point Units
arithmetic, as specified in the IEEE Standard 754. The execution unit is
broken into a separate multiply unit and a combined add/convert/divide/
square root unit. Overlap of multiplies and add/subtract is supported.
The multiplier is partially pipelined, allowing a new multiply to begin
every 6 cycles.
floating-point exceptions while allowing both overlapped and pipelined
operations. Precise exceptions are extremely important in mission-crit-
ical environments, such as ADA, and highly desirable for debugging in
any environment.
subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats, and
floating-point compare.These operations comply with IEEE Standard
754. Double precision operations are not directly supported; attempts to
execute double-precision floating point operations, or refer directly to
double-precision registers, result in the RC4650 signalling a “trap” to the
CPU, enabling emulation of the requested function. Table 2 gives the
latencies of some of the floating-point instructions in internal processor
cycles.
IDT79RC4650™
The RC4650 floating-point execution units perform single precision
As in the IDT79RC64475, the RC4650 maintains fully precise
The floating-point unit’s operation set includes floating-point add,
ADD
SUB
MUL
DIV
SQRT
CMP
FIX
FLOAT
ABS
MOV
NEG
LWC1
SWC1
Operation
Table 2 Floating-Point Operation
4
4
8
32
31
3
4
6
1
1
1
2
1
Instruction Latency
4 of 25
Floating-Point General Register File
ters. These registers are used as source or target registers for the
single-precision operations. References to these registers as 64-bit
registers (as supported in the RC64475) will cause a trap to be
signalled.
for determining configuration and revision information for the copro-
cessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
System Control Co-Processor (CP0)
sible for the virtual to physical address translation and cache protocols,
the exception control system, and the diagnostics capability of the
processor. In the MIPS architecture, the system control co-processor
(and thus the kernel software) is implementation dependent.
RC4700—have been implemented. These changes are designed to
simplify memory management, facilitate debug, and speed real-time
processing.
System Control Co-Processor Registers
registers on-chip. These registers provide the path through which the
virtual memory system’s address translation is controlled, exceptions
are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RC4650
includes registers to implement a real-time cycle counting facility, which
aids in cache diagnostic testing, assists in data error detection, and
facilitates software debug. Alternatively, this timer can be used as the
operating system reference timer, and can signal a periodic interrupt.
Table 3 shows the CP0 registers of the RC4650.
Number
0
1
2
3
4-7, 10, 20-
25, 29, 31
8
9
11
12
13
The floating-point register file is made up of thirty-two 32-bit regis-
The floating-point control register space contains two registers; one
The system control co-processor in the MIPS architecture is respon-
In the RC4650, significant changes in CP0—relative to the
The RC4650 incorporates all system control co-processor (CP0)
Table 3 RC4650 CPO Registers (Page 1 of 2)
IBase
IBound
DBase
DBound
—
BadVAddr Virtual address on address exceptions
Count
Compare
Status
Cause
Name
Instruction address space base
Instruction address space bound
Data address space base
Data address space bound
Not used
Counts every other cycle
Generate interrupt when Count = Compare
Miscellaneous control/status
Exception/Interrupt information
Function
April 10, 2001