CS80C286-12 Intersil, CS80C286-12 Datasheet - Page 21

• Manufacturer Part Number: CS80C286-12
• Description: IC CPU 16BIT 5V 12.5MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-12

• Processor Type: 80C286 16-Bit
• Speed: 12.5MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The LGDT and LLDT instructions load the base and limit of
the global and local descriptor tables. LGDT and LLDT are
privileged, i.e. they may only be executed by trusted pro-
grams operating at level 0. The LGDT instruction loads a six
byte field containing the 16-bit table limit and 24-bit physical
base address of the Global Descriptor Table as shown in
Figure 15. The LDT instruction loads a selector which refers
to a Local Descriptor Table descriptor containing the base
address and limit for an LDT, as shown in Table 11.
Interrupt Descriptor Table
The protected mode 80C286 has a third descriptor table,
called the Interrupt Descriptor Table (IDT) (see Figure 16),
used to define up to 256 interrupts. It may contain only task
gates, interrupt gates and trap gates. The IDT (Interrupt
Descriptor Table) has a 24-bit physical base and 16-bit limit
register in the CPU. The privileged LlDT instruction loads
these registers with a six byte value of identical form to that
of the LGDT instruction (see Figure 16 and Protected Mode
lnitialization).
References to IDT entries are made via INT instructions, exter-
nal interrupt vectors, or exceptions. The IDT must be at least
256 bytes in size to allocate space for all reserved interrupts.
FIGURE 14. LOCAL AND GLOBAL DESCRIPTOR TABLE
FIGURE 15. GLOBAL DESCRIPTOR TABLE AND INTERRUPT
† MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES
PROGRAM INVISIBLE
23
23
FROM LDT DESCR
(AUTOMATICALLY
24-BIT PHYS AD
24-BIT PHYS AD
15
+5
+3
+1
WITHIN GDT)
15
15
GDT BASE
LDT BASE
LOADED
SELECTOR
7
15
GDT LIMIT
LDT LIMIT
CPU
DESCR
DEFINITION
DESCRlPTOR TABLE DATA TYPE
LDT
RESERVED †
0
0
0
BASE
LIMIT
8
0 7
15 - 0
7
15 - 0
BASE
MEMORY
LDT
LDT
23 - 16
1
n
0
0
CURRENT
LDT
+4
+2
0
GDT
80C286
21
Privilege
The 80C286 has a four-level hierarchical privilege system
which controls the use of privileged instructions and access
to descriptors (and their associated segments) within a task.
Four-level privilege, as shown in Figure 17, is an extension
of the users/supervisor mode commonly found in minicom-
puters. The privilege levels are numbered 0 through 3. Level
0 is the most privileged level. Privilege levels provide protec-
tion within a task. (Tasks are isolated by providing private
LDT’s for each task.) Operating system routines, interrupt
handlers, and other system software can be included and
protected within the virtual address space of each task using
the four levels of privilege. Each task in the system has a
separate stack for each of its privilege levels.
Tasks, descriptors, and selectors have a privilege level
attribute that determines whether the descriptor may be
used. Task privilege affects the use of instructions and
descriptors. Descriptor and selector privilege only affect
access to the descriptor.
NOTE: PL becomes numerically lower as privilege level increases.
CPU
ENFORCED
SOFTWARE
INTERFACES
HIGH SPEED
OPERATING
SYSTEM
INTERFACE
FIGURE 16. INTERRUPT DESCRIPTOR TABLE DEFINITION
23
15
IDT BASE
FIGURE 17. HIERARCHICAL PRIVILEGE LEVELS
IDT LIMIT
CPU
0
0
OS EXTENSIONS
APPLICATIONS
PRIVILEGED
INTERRUPT #n-1
SERVICES
INTERRUPT #n
INTERRUPT #1
INTERRUPT #0
SYSTEM
KERNAL
PL = 0
GATE FOR
GATE FOR
GATE FOR
GATE FOR
MOST
MEMORY
PL = 1
PL = 2
INTERRUPT
DESCRIPTOR
TABLE
(IDT)
PL = 3