A80960KB20 Intel, A80960KB20 Datasheet - Page 15

• Manufacturer Part Number: A80960KB20
• Description: IC MPU I960KB 20MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960KB20

• Processor Type: i960
• Features: KB suffix, 32-Bit, 512 Byte Cache
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803516

BADAC
RESET
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
BE3:0
HOLD
HLDA
CACHE
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
NAME
NAME
TYPE
TYPE
O.D.
T.S.
T.S.
O
O
O
Table 5. 80960KB Pin Description: Support Signals (Sheet 1 of 2)
I
I
I
Table 4. 80960KB Pin Description: L-Bus Signals (Sheet 2 of 2)
BAD ACCESS, if asserted in the cycle following the one in which the last READY
of a transaction is asserted, indicates that an unrecoverable error has occurred
on the current bus transaction or that a synchronous load/store instruction has not
been acknowledged.
During system reset the BADAC signal is interpreted differently. If the signal is
high, it indicates that this processor will perform system initialization. If it is low,
another processor in the system will perform system initialization instead.
RESET clears the processor’s internal logic and causes it to reinitialize.
During RESET assertion, the input pins are ignored (except for BADAC and
IAC/INT
other output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET.
The HIGH to LOW transition of RESET should occur after the rising edge of both
CLK2 and the external bus clock and before the next rising edge of CLK2.
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are
used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to
LAD7:0.
The byte enables are provided in advance of data:
Byte enables asserted during T
Byte enables asserted during T
(the word to be transmitted following the next assertion of READY).
Byte enables that occur during T
READY are undefined. Byte enables are latched on-chip and remain constant
from one T
For reads, byte enables specify the byte(s) that the processor will actually use.
L-Bus agents are required to assert only adjacent byte enables (e.g., asserting
just BE0 and BE2 is not permitted) and are required to assert at least one byte
enable. Address bits A
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it floats its
three-state bus lines and open-drain control lines, asserts HLDA and enters the
T
T
HOLD ACKNOWLEDGE: Notifies an external bus master that the processor has
relinquished control of the bus.
CACHE indicates when an access is cacheable during a T
asserted during any synchronous access, such as a synchronous load or move
instruction used for sending an IAC message. The CACHE signal floats to a high
impedance state when the processor is idle.
i
h
or T
state. When HOLD deasserts, the processor deasserts HLDA and enters the
a
state.
0
), the three-state output pins are placed in a high impedance state and
d
cycle to the next when READY is not asserted.
0
and A
1
a
d
can be decoded externally from the byte enables.
d
DESCRIPTION
specify the bytes of the first data word.
DESCRIPTION
specify the bytes of the next data word, if any
cycles that precede the last assertion of
a
cycle. It is not
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