Z8S18033VSC Zilog, Z8S18033VSC Datasheet - Page 60
Z8S18033VSC
Manufacturer Part Number
Z8S18033VSC
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Datasheet
1.Z8S18010PSG.pdf
(71 pages)
Specifications of Z8S18033VSC
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3116
Available stocks
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Part Number
Manufacturer
Quantity
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For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
Table 16 indicates all DMA transfer mode combinations of
fers are not implemented, 12 combinations are available.
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, two automatic transfer timing modes are se-
lectable: burst (
,
* Includes memory mapped I/O.
,
, and
. Because I/O to/from I/O trans-
) and cycle steal (
When chan-
).
completes (as indicated by the byte count register = ). In
cycle steal mode, the CPU is provided a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer ignoring
is cleared to
0
during
.
ZiLOG
.