PRIXP420BB Intel, PRIXP420BB Datasheet - Page 37

• Manufacturer Part Number: PRIXP420BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP420BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 866260

Intel
Table 8.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
PCI Controller (Sheet 2 of 2)
PCI_REQ_N[0]
PCI_GNT_N[3:1]
PCI_GNT_N[0]
PCI_INTA_N
PCI_CLKIN
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Intel
®
Reset
Post
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
VI
Z
Z
Z
Z
Type
O/D
I/O
I/O
O
I
†
Table 5 on page
PCI arbitration request:
Should be pulled high with a 10-KΩ resistor, when the PCI bus is
not being utilized in the system.
PCI arbitration grant: Generated by the internal PCI arbiter to
allow an agent to claim control of the PCI bus.
PCI arbitration grant:
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI interrupt: Used to request an interrupt.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Clock: provides timing for all transactions on PCI. All PCI
signals — except INTA#, INTB#, INTC#, and INTD# — are
sampled on the rising edge of CLK and timing parameters are
defined with respect to this edge. The PCI clock rate can operate
at up to 66 MHz.
Should be pulled high
utilized in the system.
• When configured as an input (PCI arbiter enabled), the
• When configured as an output (PCI arbiter disabled), the pin
• When configured as an output (PCI arbiter enabled), the
• When configured as an input (PCI arbiter disabled), the pin
internal PCI arbiter will allow an agent to request the PCI
bus.
will be used to request access to the PCI bus from an
external arbiter.
internal PCI arbiter to allow an agent to claim control of the
PCI bus.
will be used to claim access of the PCI bus from an external
arbiter.
33.
††
with a 10-KΩ resistor when not being
Description
Datasheet
37