ATF16V8B-10JU Atmel, ATF16V8B-10JU Datasheet - Page 10

IC PLD 10NS 20PLCC

ATF16V8B-10JU

Manufacturer Part Number
ATF16V8B-10JU
Description
IC PLD 10NS 20PLCC
Manufacturer
Atmel
Datasheet

Specifications of ATF16V8B-10JU

Programmable Type
EE PLD
Number Of Macrocells
8
Voltage - Input
5V
Speed
10ns
Mounting Type
Surface Mount
Package / Case
20-PLCC
Delay Time
10 ns
Logic Family
ATF16V8B
Maximum Operating Frequency
83 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
8
Number Of Programmable I/os
20
Operating Supply Voltage
5 V
Supply Current
55 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF16V8B-10JU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATF16V8B-10JU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
11.1
10
ATF16V8B Registered Mode
ATF16V8B/BQ/BQL
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis-
ters are required. Each macrocell can be configured as either a registered or combinatorial
output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin,
and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term.
For a combinatorial output or I/O, the output enable is controlled by a product term, and seven
product terms are allocated to the sum term. When the macrocell is configured as an input, the
output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices
can be emulated using this mode:
16R8
16R6
16R4
Figure 11-1. Registered Configuration for Registered Mode
Notes:
Figure 11-2. Combinatorial Configuration for Registered Mode
Notes:
1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the reg-
2. The development software configures all the architecture control bits and checks for proper pin
1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin
16RP8
16RP6
16RP4
istered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE.
usage automatically.
usage automatically.
(1)(2)
(1)(2)
0364J–PLD–7/05

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