UDA1344TS/N2,512 NXP Semiconductors, UDA1344TS/N2,512 Datasheet - Page 19

• Manufacturer Part Number: UDA1344TS/N2,512
• Description: IC AUDIO CODEC W/DSP 28-SSOP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1344TS/N2,512

• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 2.7 V ~ 3.6 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 55 KSPS
• Interface Type: Serial (I2S)
• Resolution: 20 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/ 2 DAC
• Supply Current: 9 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1156-5; 935261790512; UDA1344TSDB

NXP Semiconductors
TIMING
V
otherwise specified.
2001 Jun 29
System clock input (see Fig.7)
T
t
t
Serial interface input/output data (see Fig.8)
f
T
t
t
t
t
t
t
t
t
t
t
t
L3 interface input (see Figs 4 and 5)
T
t
t
t
t
t
t
t
t
t
DDD
CWH
CWL
BCK
BCKH
BCKL
r
f
su(WS)
h(WS)
su(DATAI)
h(DATAI)
h(DATAO)
d(DATAO−BCK)
d(DATAO−WS)
CLK(L3)H
CLK(L3)L
su(L3)A
h(L3)A
su(L3)D
h(L3)D
stp(L3)
su(L3)DA
h(L3)DA
sys
cy(BCK)
cy(CLK)L3
SYMBOL
Low-voltage low-power stereo audio
CODEC with DSP features
= V
DDA
= V
system clock cycle time
system clock HIGH time
system clock LOW time
bit clock frequency
bit clock cycle time
bit clock HIGH time
bit clock LOW time
rise time
fall time
word select set-up time
word select hold time
data input set-up time
data input hold time
data output hold time
data output to bit clock delay
data output to word select delay
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time for address mode
L3MODE hold time for address mode
L3MODE set-up time for data transfer
mode
L3MODE hold time for data transfer mode
L3MODE stop time
L3DATA set-up time in data transfer and
address mode
L3DATA hold time in data transfer and
address mode
DDO
= 2.7 to 3.6 V; T
PARAMETER
amb
= −40 to +85 °C; R
19
f
f
f
f
f
f
f
T
sample frequency
from BCK falling edge −
from WS edge for
MSB-justified format
sys
sys
sys
sys
sys
sys
sys
cy(s)
L
= 5 kΩ; all voltages referenced to ground; unless
= 256f
= 384f
= 512f
< 19.2 MHz
≥ 19.2 MHz
< 19.2 MHz
≥ 19.2 MHz
CONDITIONS
= cycle time of
s
s
s
0
190
190
78
52
39
0.30T
0.40T
0.30T
0.40T
−
100
100
−
−
20
10
20
0
−
500
250
250
190
190
190
190
30
T
------------ -
MIN.
64
cy(s)
sys
sys
sys
sys
88
59
44
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TYP.
UDA1344TS
Product specification
−
−
−
0.70T
0.60T
0.70T
0.60T
64f
−
−
−
20
20
−
−
−
−
−
80
80
−
−
−
−
−
−
−
−
−
−
MAX.
s
sys
sys
sys
sys
ns
ns
ns
ns
ns
ns
ns
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT