PCA9564D,118 NXP Semiconductors, PCA9564D,118 Datasheet - Page 25

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PCA9564D,118

Manufacturer Part Number
PCA9564D,118
Description
IC CTRL PARALLEL/I2C BUS 20SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9564D,118

Package / Case
20-SOIC (7.5mm Width)
Controller Type
Parallel Bus to I²C Bus Controller
Interface
I²C
Voltage - Supply
2.3 V ~ 3.6 V
Current - Supply
6mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4001 - DEMO BOARD FOR PCA9564
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935272894118
PCA9564D-T
PCA9564D-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9564D,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns
3. Test conditions for outputs: C
4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
5. Upon reset, the full delay will be the sum of t
Philips Semiconductors
AC CHARACTERISTICS (2.5 VOLT)
V
NOTES:
2006 Sep 01
Reset Timing (See Figure 19)
Bus Timing (See Figure 20, 21)
CC
SYMBOL
Parallel bus to I
maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.
pullup to V
t
t
RES
= 2.5 V
WRES
t
t
t
RWD
REC
t
t
t
t
t
t
t
t
RW
AS
AH
CS
CH
DD
DF
DS
DH
4,5
DD
0.2 V, T
Reset pulse width
Time to reset
Reset recovery time
A0–A1 setup time to RD, WR LOW
A0–A hold time from RD, WR LOW
CE setup time to RD, WR LOW
CE Hold time from RD, WR LOW
WR, RD pulse width (low time)
Data valid after RD and CE LOW
Data bus floating after RD or CE HIGH
Data bus setup time before WR or CE HIGH (write cycle)
Data hold time after WR HIGH
High time between read and/or write cycles
.
amb
= –40 to +85 C, unless otherwise specified. (See page 24 for 3.3 V.)
2
C-bus controller
L
= 50 pF, R
L
= 500 , except open drain outputs. Test conditions for open drain outputs: C
1, 2, 3
RES
PARAMETER
and the RC time constant of the SDA and SCL bus.
25
Min
250
10
12
0
0
9
0
0
9
8
0
LIMITS
Max
22
17
L
PCA9564
= 50 pF, R
Product data sheet
UNIT
L
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 1 k

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