MFRC52201HN1,157 NXP Semiconductors, MFRC52201HN1,157 Datasheet - Page 65

• Manufacturer Part Number: MFRC52201HN1,157
• Description: IC SMART CARD READER
• Manufacturer: NXP Semiconductors

Specifications of MFRC52201HN1,157

• Controller Type: Smart Card Interface
• Interface: SPI
• Voltage - Supply: 1.6 V ~ 3.6 V
• Current - Supply: 60mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280547157; MFRC52201HN1; MFRC52201HN1

NXP Semiconductors
12. FIFO Buffer
112132
Product data sheet
12.1 Overview
12.2 Accessing the FIFO Buffer
12.3 Controlling the FIFO-Buffer
12.4 Status Information about the FIFO-Buffer
An 64 × 8-bit FIFO buffer is implemented in the MFRC522. It buffers the input and output
data stream between the host and the internal state machine of the MFRC522. Thus, it is
possible to handle data streams with lengths of up to 64 bytes without taking timing
constraints into account.
The FIFO-buffer input and output data bus is connected to the register FIFODataReg.
Writing to this register stores one byte in the FIFO-buffer and increments the internal
FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents
stored at the FIFO-buffer read-pointer and decrements the FIFO-buffer read-pointer. The
distance between the write- and read-pointer can be obtained by reading the register
FIFOLevelReg.
When the μ-Controller starts a command, the MFRC522 may, while the command is in
progress, access the FIFO-buffer according to that command. Physically only one
FIFO-buffer is implemented, which can be used in input- and output direction. Therefore
the μ-Controller has to take care, not to access the FIFO-buffer in an unintended way.
Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be
reset by setting the bit FlushBuffer in the register FIFOLevelReg to 1. Consequently, the
FIFOLevel bits are set to logic 0, the bit BufferOvfl in the register ErrorReg is cleared, the
actually stored bytes are not accessible any more and the FIFO-buffer can be filled with
another 64 bytes again.
The host may obtain the following data about the FIFO-buffers status:
The MFRC522 can generate an interrupt signal
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Number of bytes already stored in the FIFO-buffer: FIFOLevel in register
FIFOLevelReg
Warning, that the FIFO-buffer is almost full: HiAlert in register Status1Reg
Warning, that the FIFO-buffer is almost empty: LoAlert in register Status1Reg
Indication, that bytes were written to the FIFO-buffer although it was already full:
BufferOvfl in register ErrorReg. BufferOvfl can be cleared only by setting bit
FlushBuffer in the register FIFOLevelReg.
If LoAlertIEn in register CommIEnReg is set to logic 1 it will activate pin IRQ when
LoAlert in the register Status1Reg changes to 1.
If HiAlertIEN in register CommIEnReg is set to logic 1 it will activate pin IRQ when
HiAlert in the register Status1Reg changes to 1.
Rev. 3.2 — 22 May 2007
Contactless Reader IC
MFRC522
© NXP B.V. 2007. All rights reserved.
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