Z8023016PSG Zilog, Z8023016PSG Datasheet - Page 79

• Manufacturer Part Number: Z8023016PSG
• Description: IC 16MHZ Z8000 CMOS ESCC 40-DIP
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z8023016PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z85230/Z80230
Product Specification
74
A/B, D/C
Address Valid
INTACK
CE
Address Valid
D7–D0
WR
Figure 21. Write Cycle Timing (Z85230)
Z85230 Interrupt Acknowledge Cycle Timing
Figure 22
illustrates Interrupt Acknowledge Cycle timing. Between the time INTACK
goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle.
If there is an interrupt pending in the ESCC and IEI is High when RD falls, the Acknowl-
edge cycle is intended for the ESCC. In this case, the ESCC may be programmed to
respond to RD Low by placing its interrupt vector on D7–D0. It then sets the appropriate
IUS latch internally. If the external daisy chain is not used, then AC Parameter 38 is
required to settle the interrupt priority daisy chain internal to the ESCC. If the external
daisy chain is used, follow the equation in AC Characteristics Note 5
(Table 46
on
page 89) to calculate the required daisy chain settle time.
INTACK
RD
D7–D0
Vector
Figure 22. Interrupt Acknowledge Cycle Timing (Z85230)
PS005303-0907
Z80230 Interface Timing