EN63A0QI-E Enpirion, EN63A0QI-E Datasheet - Page 3

• Manufacturer Part Number: EN63A0QI-E
• Description: Power Management Development Tools EN63A0QI Eval Board 12A Hi Eff Buck Con
• Manufacturer: Enpirion
• Type: DC/DC Switching Converters, Regulators & Controllersr

Specifications of EN63A0QI-E

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.375 V to 6.6 V
• Output Current: 12 A
• Product: Power Management Development Tools
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EN63A0QI

©Enpirion 2012 all rights reserved, E&OE
07077
30-31,70-
32-38
39-51
PIN
71
54
55
56
57
58
59
60
61
62
63
64
65
66
68
69
77
ENABLE
VSENSE
NC(SW)
NAME
EAOUT
S_OUT
FQADJ
EN_PB
PGND
BGND
AGND
PGND
VDDB
PVIN
AVIN
S_IN
POK
VFB
M/S
SS
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device damage.
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Refer to VOUT, PVIN descriptions and Layout Recommendation for
more details.
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 36 to 38.
Internal regulated voltage used for the internal control circuitry. Decouple with an optional
0.1µF capacitor to BGND for improved efficiency. This pin may be left floating if board space is
limited.
Ground for VDDB. Refer to pin 46 description.
Digital input. A high level on the M/S pin will make this EN63A0QI a Slave and the S_IN will
accept the S_OUT signal from another EN63A0QI for parallel operation. A low level on the M/S
pin will make this device a Master and the switching frequency will be phase locked to an
external clock. Leave this pin floating if it is not used.
Digital output. A low level on the M/S pin will make this EN63A0QI a Master and the internal
switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of
another EN63A0QI device for parallel operation. Leave this pin floating if it is not used.
POK is a logic level high when VOUT is within -10% to +20% of the programmed output
voltage (0.9V
with a nominal value of 120k .
Device enable pin. A high level or floating this pin enables the device while a low level disables
the device. A voltage ramp from another power converter may be applied for precision enable.
Refer to Power Up Sequencing.
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is
sequencing.
The quiet ground for the control circuits. Connect to the ground plane with a via right next to the
pin.
Ternary (three states) input pin. Floating this pin disables parallel operation. A low level
configures the device as Master and a high level configures the device as a Slave. A R
resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional
Description section for R
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor (C
resistor (R1) are required parallel to the upper feedback resistor (R
regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB
floating.
Error amplifier output. Allows for customization of the control loop. May be left floating.
A soft-start capacitor is connected between this pin and AGND. The value of the capacitor
controls the soft-start interval. Refer to Soft-Start in the Functional Description for more details.
This pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect
VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low.
Frequency adjust pin. This pin must have a resistor to AGND which sets the free running
frequency of the internal oscillator.
Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up
under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is
pulled high internally. Enable pre-bias feature is not available for parallel operations.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes. Refer to Layout Recommendation section.
OUT_NOM
≤ V
EXT
OUT
values. Also see S_IN and S_OUT pin descriptions.
≤ 1.2V
Enpirion Confidential
May 9, 2012
OUT_NOM
FUNCTION
). This pin has an internal pull-up resistor to AVIN
A
www.enpirion.com, Page 3
). The output voltage
EN63A0QI
A
) and
EXT
Rev: C