FDC37B727-NS SMSC, FDC37B727-NS Datasheet - Page 195

• Manufacturer Part Number: FDC37B727-NS
• Description: IC CTRLR SUPER I/O ENH 128-QFP
• Manufacturer: SMSC

Specifications of FDC37B727-NS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1005

GP1
Default = 0x00
on Vbat POR
GP5
Default = 0x00
on Vbat POR
GP6
Default = 0x00
on Vbat POR
NAME
REG INDEX
0xFA
0xF6
0xF9
signal generated by the Force Timeout Bit.
Bit[4] Reserved. Set to 0.
Bit[5] Stop_Cnt: This is used to terminate Delay 2 (Note
Bit[6] Restart_Cnt: This is used to restart Delay 2 (Note
Bit[7] SPOFF: This is used to force a software power
Note 1: This delay is programmable via the Delay 2
Time Set Register at Logical Device 8, 0xB8.
This register is used to read the value of the GPIO
pins.
Bit[0]: GP10
Bit[1]: GP11
Bit[2]: GP12
Bit[3]: GP13
Bit[4]: GP14
Bit[5]: GP15
Bit[6]: GP16
Bit[7]: GP17
This register is used to read the value of the GPIO
pins.
Bit[0]: GP50
Bit[1]: GP51
Bit[2]: GP52
Bit[3]: GP53
Bit[4]: GP54
Bit[7:5]: Reserved
This register is used to read the value of the GPIO
pins.
Bit[0]: GP60
Bit[1]: GP61
Bit[2]: GP62
Bit[3]: GP63
1) without generating a power down. This is
used if the software determines that the power
down should be aborted. When read, this bit
indicates the following: Stop_Cnt = 0; Counter
running Stop_Cnt = 1; Counter Stopped. Note:
The write is self clearing.
1) from the button input to the generation of the
power down. When restarted, the count will
start over and delay the power down for the
time that Delay 2 is set for (Default=500msec).
The software can continue to do this
indefinately with out allowing a powerdown.
This bit is self clearing. 1=Restart;
Automatically cleared.
down. This bit is self clearing.
196
DEFINITION
STATE