PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 3

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

1.1.1
1.2
2137D–HIREL–08/05
Features
General Parameters
The following list provides a summary of the general parameters of the PC107A:
Technology
Die size
Transistor count
Logic design
Package
Core power supply
I/O power supply
The PC107A provides an integrated high-bandwidth, high-performance interface between up to
two 60x processors, the PCI bus, and main memory. This section summarizes the features of
the PC107A. Major features of the PC107A are as follows:
• Memory Interface
• 32-bit PCI Interface Operating up to 66 MHz
– 64-/32-bit 100 MHz bus
– Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM
– High-bandwidth bus (32-/64-bit data bus) to DRAM
– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices, and up to
– Supports 1M byte to 1 Gbyte DRAM memory
– 144M bytes of ROM space
– 8-, 32-, or 64-bit ROM
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
– PCI 2.1-compliant
– PCI 5.0V tolerance
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
four banks of 256 Mbit SDRAM devices
programmable address strobe timing
0.29 µm CMOS, five-layer metal
50 mm
Fully-static
Surface mount 503 Plastic Ball Grid Array (C4/PBGA)
2.5 ±5% V DC (nominal; see
recommended operating conditions)
3.0 to 3.6V DC
0.96 million
2
Table 5-2 on page 12
PC107A
for
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