DP83955AV National Semiconductor, DP83955AV Datasheet - Page 22

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

M identification must be performed across all the LERICs in
PORT N identification is performed when the repeater is in
MIT COLLISION state In order for the arbitration chain to
5 0 Functional Description
Methods of LERIC Cascading
In order to build multi-LERIC repeaters PORT N and PORT
the system Inside each LERIC the PSMs are arranged in a
logical arbitration chain where Port 1 is the highest and Port
7 the lowest
The top of the chain the input to Port 1 is accessible to the
user via the LERIC’s ACKI input pin The output from the
bottom of the chain becomes the ACKO output pin In a
single LERIC system PORT N is defined as the highest port
in the arbitration chain with receive or collision activity
the IDLE state PORT M is defined as the highest port in the
chain with a collision when the repeater leaves the TRANS-
function all that needs to be done is to tie the ACKI signal
to a logic high state In multi-LERIC systems there are
two methods to propagate the arbitration chain between
LERICs
The first and most straightforward way is to extend the arbi-
tration chain by daisy-chaining the ACKI –ACKO signals be-
tween LERICs In this approach one LERIC is placed at the
top of the chain (its ACKI input is tied high) then the ACKO
signal from this LERIC is sent to the ACKI input of the next
LERIC and so on This arrangement is simple to implement
but it places some topological restrictions upon the repeater
system In particular when the repeater is constructed using
a backplane with removable printed circuit boards contain-
ing the LERICs if one of the boards is removed then the
ACKI –ACKO chain will be broken and the repeater will not
operate correctly
The second method of PORT N or M identification avoids
this problem This second technique relies on an external
parallel arbiter which monitors all of the LERICs’ ACKO sig-
nals and responds to the LERIC with the highest priority In
this scheme each LERIC is assigned with a priority level
One method of doing this is to assign a priority number
which reflects the position of a LERIC board on the repeater
backplane (i e its slot number) When a LERIC experiences
receive activity and the repeater system is in the IDLE state
the LERIC board will assert ACKO External arbitration logic
drives the identification number onto an arbitration bus and
the LERIC containing PORT N will be identified An identical
procedure is used in the TRANSMIT COLLISION state to
identify PORT M This parallel means of arbitration is not
subject to the problems caused by missing boards (i e
empty slots in the backplane) The logic associated with
asserting this arbitration vector in the various packet repeti-
tion scenarios could be implemented in PAL or GAL type
devices
To perform PORT N or M arbitration both of the above
methods employ the same signals ACKI ACKO and
ACTN
(Continued)
22
LISION states)
Figure 5-3 shows two LERICs A and B daisy-chained to-
The Inter-LERIC bus allows multi-LERIC operations to be
performed in exactly the same manner as if there is only a
single LERIC in the system The simplest way to describe
the operation of Inter-LERIC bus is to see how it is used in a
number of common packet repetition scenarios Throughout
this description the LERICs are presumed to be operating in
external transceiver mode This is advantageous for the ex-
planation since the receive transmit and collision signals
from each network segment are observable In internal
transceiver mode this is not the case since the collision
signal for the non-AUI ports is derived by the transceivers
inside the LERIC
5 3 EXAMPLES OF PACKET REPETITION SCENARIOS
Data Repetition
The simplest packet operation performed over the Inter-
LERIC Bus is data repetition In this operation a data packet
is received at one port and transmitted to all other seg-
ments
The first task to be performed is PORT N identification This
is an arbitration process performed by the Port State Ma-
chines in the system In situations where two or more ports
simultaneously receive packets the Inter-LERIC bus oper-
ates by choosing one of the active ports and forcing the
others to transmit data This is done to faithfully follow the
IEEE specification’s allowed exit paths from the IDLE state
(i e to the SEND PREAMBLE PATTERN or RECEIVE COL-
The packet begins with a preamble pattern derived from the
LERIC’s on chip jam preamble generator The data re-
ceived at PORT N is directed through the receive multiplex-
er to the PLL decoder Once phase lock has been achieved
the decoded data in NRZ format with its associated clock
and enable signals are asserted onto the IRD IRE and IRC
Inter-LERIC bus lines This serial data stream is received
from the bus by all LERICs in the repeater and directed to
their Elasticity Buffers Logic circuits monitor the data
stream and look for the Start of Frame Delimiter (SFD)
When this has been detected data is loaded into the elastic-
ity buffer for later transmission This will occur when suffi-
cient preamble has been transmitted and certain internal
state machine operations have been fulfilled
gether with LERIC A positioned at the top of the chain A
packet is received at port B1 of LERIC B and is then repeat-
ed by the other ports in the system Figure 5-4 shows the
functional timing diagram for this packet repetition repre-
sented by the signals shown in Figure 5-3 In this example
only two ports in the system are shown obviously the other
ports also repeat the packet It also indicates the operation
of the LERICs’ state machines in so far as can be seen by
observing the Inter-LERIC bus For reference the repeat-
er’s state transitions are shown in terms of the states de-
fined by the IEEE specification The location (i e which port
it is) of PORT N is also shown The following section
describes the repeater and Inter-LERIC bus transitions
shown in Figure 5-4