DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 63

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

5 0 Bus Interface
Latched Bus Retry is set though the SONIC will not retry
until the BR bit in the ISR (see Section 4 3 6) has been reset
and BRT is deasserted BRT has precedence of terminating
a memory cycle over DSACK0 1 STERM or RDYi
BRT may be sampled synchronously or asynchronously by
setting the EXBUS bit in the DCR (see Section 4 3 2) If
synchronous Bus Retry is set BRT is sampled on the rising
edge of T2 If asynchronous Bus Retry is set BRT is double
synchronized from the falling edge of T1 The asynchronous
setup time does not need to be met but doing so will guar-
antee that the bus exception will occur in the current bus
cycle instead of the next bus cycle Asynchronous Bus Re-
try may only be used when the SONIC is set to asynchro-
nous mode
Note 1 The deassertion edge of HOLD is dependent on the PH bit in the
Note 2 If Latched Bus Retry is set BRT need only satisfy its setup time
Note 3 If DSACK0 1 STERM or RDYi remain asserted after BRT the next
5 4 7 Slave Mode Bus Cycle
The SONIC’s internal registers can be accessed by one of
two methods (BMODE
ods the SONIC is a slave on the bus This section de-
scribes the SONIC’s slave mode bus operations
5 4 7 1 Slave Cycle for BMODE
The system accesses the SONIC by driving SAS CS SRW
and RA
SAS are asserted properly SONIC samples CS asynchro-
nously at the falling edge of each BSCK SAS signal can be
asserted anytime as long as it is before the next falling edge
of the clock that the CS is sampled on
The register address RA
SRW will be latched by the SONIC on the falling edge of the
SAS signal Once SAS and CS are asserted SMACK will be
asserted by the SONIC to signify that the SONIC has started
the slave cycle Although CS and SAS are asynchronous
inputs meeting their setup times (as shown in Figures 5-21
and 5-22 ) will guarantee that SMACK which is asserted off
DCR2 (see Section 4 3 7) Also BGACK is driven high for about
bus clock before going TRI-STATE
(the hold time is not important) Otherwise BRT must remain as-
serted until after the Th state
memory cycle may be adversely affected
k
5 0
l
SONIC will start a slave cycle once CS and
e
k
1 or BMODE
5 0
(Continued)
l
e
and the read write signal
1
e
FIGURE 5-20 Bus Exception (Bus Retry)
0) In both meth-
63
of a falling edge will be asserted 1 bus clock after the falling
edge that CS was clocked in on This is assuming that the
SONIC is not a bus master when CS was asserted If the
SONIC is a bus master then when CS is asserted the
SONIC will complete its current master bus cycle and get off
the bus temporarily (see Section 5 4 8) In this case
SMACK will be asserted maximum 5 bus clocks after the
falling edge that CS was clocked in on This is assuming
that there were no wait states in the current master mode
access Wait states will increase the time for SMACK to go
low by the number of wait states in the cycle
If the slave access is a read cycle ( Figure 5-21 ) then the
data will be driven off the same edge as SMACK If it is a
write cycle ( Figure 5-22 ) then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK In either
case DSACK0 1 are driven low 2 bus clocks after SMACK
to terminate the slave cycle For a read cycle the assertion
of DSACK0 1 indicates valid register data and for a write
cycle the assertion indicates that the SONIC has latched
the data The SONIC deasserts DSACK0 1 at the rising
edge of SAS or CS depending on which is deasserted first
The data bus is deasserted on the rising edge of SAS The
SONIC deasserts SMACK and causes DSACK0 1 to be-
come TRI-STATE on the falling edge of the BSCK that SAS
was sampled high on
Note 1 Although the SONIC responds as a 32-bit peripheral when it drives
Note 2 For multiple register accesses CS can be held low and SAS can be
Note 3 If memory request (MREQ) follows a chip select (CS) it must be
Note 4 When CS is deasserted it must remain deasserted for at least one
Note 5 The way in which SMACK is asserted due to CS is not the same as
both DSACK0 and DSACK1 low it transfers data only on lines
D
used to delimit the slave cycle In this case SMACK will be driven
low due to SAS going low since CS has already been asserted
Notice that this means SMACK will not stay asserted low during the
entire time CS is low (as is the case for MREQ Section 5 4 8)
asserted at least 2 bus clocks after CS is deasserted Both CS and
MREQ must not be asserted concurrently
bus clock
the way in which SMACK is asserted due to MREQ The assertion
of SMACK is dependent upon both CS and SAS being low not just
CS This is not the same as the case for MREQ (see Section 5 4 8)
The assertion of SMACK in these two cases should not be con-
fused
k
15 0
l
TL F 10492 – 46