DP83932CVF-25 National Semiconductor, DP83932CVF-25 Datasheet - Page 70

• Manufacturer Part Number: DP83932CVF-25
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-25

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-25

quired between the receive input pair and the AUI interface
6 0 Network Interfacing
External ENDEC When EXT
passed and the signals are provided directly to the user
Since SONIC’s on-chip ENDEC is the same as National’s
DP83910 Serial Network Interface (SNI) the interface con-
siderations discussed in this section would also apply to
using this device in the external ENDEC mode
6 1 MANCHESTER ENCODER AND
DIFFERENTIAL DRIVER
The ENDEC unit’s encoder begins operation when the MAC
section begins sending the serial data stream It converts
NRZ data from the MAC section to Manchester data for the
differential drivers (TX
first half of the bit cell contains the complementary data and
the second half contains the true data (Figure 6-3) A tran-
sition always occurs at the middle of the bit cell As long as
the MAC continues sending data the ENDEC section re-
mains in operation At the end of transmission the last tran-
sition is always positive occurring at the center of the bit
cell if the last bit is a one or at the end of the bit cell if the
last bit is a zero
The differential transmit pair drives up to 50 meters of twist-
ed pair AUI cable These outputs are source followers which
require two 270
a pulse transformer is required between the transmit pair
output and the AUI interface
The driver allows both half-step and full-step modes for
compatibility with Ethernet and IEEE 802 3 When the SEL
pin is tied to ground (for Ethernet) TX
respect to TX
tion transformer ( Figure 6-2 ) When SEL is tied to V
IEEE 802 3) TX
6 1 1 Manchester Decoder
The decoder consists of a differential receiver and a phase
lock loop (PLL) to separate the Manchester encoded data
stream into clock signals and NRZ data The differential in-
put must be externally terminated with two 39
connected in series In addition a pulse transformer is re-
To prevent noise from falsely triggering the decoder a
squelch circuit at the input rejects signals with a magnitude
less than
are decoded
FIGURE 6 3 Manchester Encoded Data Stream
b
175 mV Signals more negative than
b
a
during idle on the primary side of the isola-
pull-down resistors to ground In addition
and TX
a b
b
) In Manchester encoding the
e
are equal in the idle state
1 the internal ENDEC is by-
(Continued)
a
is positive with
TL F 10492–55
b
resistors
300 mV
CC
(for
70
6-4 and suggested crystal specifications are shown in Table
Once the input exceeds the squelch requirements the de-
coder begins operation The decoder detects the end of a
frame within one and a half bit times after the last bit of
data
6 1 2 Collision Translator
When the Ethernet transceiver (DP8392 CTI) detects a colli-
sion it generates a 10 MHz signal to the differential collision
inputs (CD
tects these inputs active its Collision translator converts the
10 MHz signal to an active collision signal to the MAC sec-
tion This signal causes SONIC to abort its current transmis-
sion and reschedule another transmission attempt
The collision differential inputs are terminated the same way
as the differential receive inputs and a pulse transformer is
required between the collision input pair and the AUI inter-
face The squelch circuitry is also similar rejecting pulses
with magnitudes less than
6 1 3 Oscillator Inputs
The oscillator inputs to the SONIC (OSCIN and OSCOUT)
can be driven with a parallel resonant crystal or an external
clock In either case the oscillator inputs must be driven with
a 20 MHZ signal The signal is divided by 2 to generate the
10 MHz transmit clock (TXC) for the MAC unit The oscilla-
tor also provides internal clock signals for the encoding and
decoding circuits
6 1 3 1 External Crystal
According to the IEEE 802 3 standard the transmit clock
(TXC) must be accurate to 0 01% This means that the os-
cillator circuit which includes the crystal and other parts
involved must be accurate to 0 01% after the clock has
been divided in half Hence when using a crystal it is nec-
essary to consider all aspects of the crystal circuit An ex-
ample of a recommended crystal circuit is shown in Figure
6-1
The load capacitors in Figure 6-4 C1 and C2 should be no
greater than 36 pF each including all stray capacitance
(see note 2 below) The resistor R1 may be required in
order to minimize frequency drift due to changes in V
R1 is required its value must be carefully selected since R1
decreases the loop gain If R1 is made too large the loop
gain will be greatly reduced and the crystal will not oscillate
If R1 is made too small normal variations in V
the oscillation frequency to drift out of specification As a
first rule of thumb the value of R1 should be made equal to
five times the motional resistance of the crystal The mo-
tional resistance of 20 MHz crystals is usually in the range
of 10
should be in the range of 50
whether or not to include R1 should be based upon mea-
sured variations of crystal frequency as each of the circuit
parameters are varied
to 30
a
and CD
This implies that reasonable values for R1
b
) of the SONIC When SONIC de-
b
175 mV
to 150
The decision of
CC
may cause
CC
If