DP83959VUL National Semiconductor, DP83959VUL Datasheet
DP83959VUL
Specifications of DP83959VUL
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DP83959VUL Summary of contents
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... Transformer 10BASE-T 10BASE-T 10BASE-T Port 1 Port 2 Port 3 ® TRI-STATE is a registered trademark of National Semiconductor Corporation. ™ ™ LERIC and Inter-LERIC are trademarks of National Semiconductor Corporation. ©1997 National Semiconductor Corporation Features Fully IEEE 802.3 Ethernet Repeater compliant Eight IEEE 802.3 10BASE-T compliant ports with on-chip transmit fi ...
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Block Diagram 2 www.national.com ...
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Table of Contents 1.0 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 ...
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... GND_LED 153 /TRAF4 154 /TRAF5 155 /TRAF6 156 GND_LED 157 /TRAF7 158 /TRAF8 159 NC 160 DP83959VUL LERIC8 160 pin PQFP Top View Order Number DP83959VUL See NS Package Number VUL160A TX8- 79 TX8+ 78 GND_P8 77 VCC_P8 76 RX8 RX8+ 73 RX0- RX0+ 72 CD0- 71 ...
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... This output should be connected directly to the AUI isolation transformer. AUI Transmit -: The AUI transmit path includes National Semiconductor's patented low power dissipation differential drivers that do not need external load resistors. ...
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Pin Descriptions (Continued) The values of the resistor/capacitor parallel source imped- ance matching networks connected to each of the 10BASE-T transmit outputs will depend upon PCB layout factors (such as track length, width, route etc.) and will have to ...
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Pin Descriptions (Continued) 4.3 STATUS LED INTERFACE All the DP83959's direct drive LED outputs can drive up to 14mA maximum. The LED outputs are intended to drive an external LED with a series current limiting resistor. The Par- tition/Link ...
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Pin Descriptions (Continued) Signal Name Type Pin # P/L_6A O (14mA 20 P/L_6B max.) 21 P/L_7A O (14mA 22 P/L_7B max.) 25 P/L_8A O (14mA 26 P/L_8B max.) 27 /TRAF1 O (14mA 150 max.) /TRAF2 O (14mA 151 max.) ...
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Pin Descriptions (Continued) Signal Name Type Pin # /PART0 O (14mA 39 max.) /GCOL O (14mA max.) /GACT O (14mA max.) 4.4 INTER-LERIC BUS INTERFACE Signal Name Type Pin # /ACKI I 32 /ACKO O 33 IRD I/O 45 ...
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Pin Descriptions (Continued) Signal Name Type Pin # /ACTN I/O (O.D.) 48 /ANYXN I/O (O.D.) 49 4.5 CLOCK INTERFACE Signal Name Type Pin # X_IN I 144 X_OUT O 145 Description Activity on Port N: The LERIC8 asserts this ...
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Pin Descriptions (Continued) 4.6 REGISTER/CONFIGURATION INTERFACE Signal Name Type Pin # RA4 I/O 63 RA3 62 RA2 61 RA1 60 RA0 /READY O ...
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Pin Descriptions (Continued) Signal Name Type Pin # RST_INT/EXT I 143 4.7 MISCELLANEOUS PINS Signal Name Type Pin # DEF/OPT I 29 TEST_1 I 28 TEST_2 I 103 TEST_3 O 104 TEST_4 I 111 TEST_5 I 102 TEST_EN I ...
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Pin Descriptions (Continued) 4.8 POWER AND GROUND PINS The LERIC8 has power and ground (V CC each of the major functional blocks of the device. This sec- tion describes the pairing and decoupling requirements of the power and ground ...
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Functional Description The DP83959 LERIC8 consists of the following functional blocks, each of which is described in the sections that follow: Repeater Main State Machine & Timers Port State Machines Receive Multiplexer Manchester Decoder Elasticity Buffer Transmit De-Multiplexer & ...
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Functional Description The DP83959 has a 32 bit elasticity buffer (FIFO) in the transmit path prior to the transmit de-multiplexer. This en- ables the DP83959 to synchronize data packets to its own local clock prior to transmission and regenerate ...
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Functional Description Optionally, configuration information can be loaded into the device at reset from values set by pull-up and/or pull-down resistors on the D[3:0] and RA[4:0] pins. See Section 5.12 for more details. The rising edge of the selected ...
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Functional Description DP83959 LERIC8 P/L_1A P/L_1B P/L_2A P/L_2B P/L_3A P/L_3B P/L_4A P/L_4B P/L_5A P/L_5B P/L_6A P/L_6B P/L_7A P/L_7B P/L_8A P/L_8B /TRAF1 /TRAF2 /TRAF3 /TRAF4 /TRAF5 /TRAF6 /TRAF7 /TRAF8 /PART0 /GCOL /GACT /ALERT Figure 5. DP83959 Direct Drive LED Connections ...
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Functional Description 5.11 PORT STATUS LEDS The eight 10BASE-T Port Partition Status/Link OK Status bi-color LED outputs have the functionality given in Table 2. The representational logic of this function is given in Figure 6. This logic is repeated ...
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Functional Description Table 3 Default/Optional Mode Configuration Parameter Selection Effect When Pin Function Bit = Reserved Not Permitted D3 EPOLSW Not Selected RA0 Reserved Not Permitted RA1 /TXONLY Selected RA2 /CCLIM ...
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Functional Description Pin Mnemonic D0 ACOL Any Collision: Asserted when a collision occurs on any of this LERIC8's ports. D1 AREC Any Receive: Asserted when any of this LERIC8's ports experiences a data or collision packet on its receive ...
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Functional Description DP83959 LERIC8 TX0+ TX0- RX0+ RX0- CD0+ CD0- DP83959 * Starting point values - will need to be adjusted depending on layout, transformer LERIC8 module and other application variations. TXn+ * 820pF TXn- * 820pF RXn+ 49.9 ...
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LERIC8 Registers 6.1 REGISTER ADDRESS MAP The LERIC8's register address map is shown below. Since the data path is only a nibble wide interface, each register has two addresses, with the most significant address bit (RA4) used to select ...
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LERIC8 Registers (Continued) 6.2 LERIC8 STATUS REGISTER Address: RA4 - RA0 0 0000 - lower nibble 1 0000 - upper nibble Bit Bit Name Access D0 /ACOL D1 /AREC D2 /JAB D3 /APART D4 Reserved D5 Reserved D6 Reserved ...
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LERIC8 Registers (Continued) 6.3 PORT 0 (AUI) STATUS/CONFIGURATION REGISTER Address: RA4 - RA0 0 0001 - lower nibble 1 0001 - upper nibble Bit Bit Name Access D0 Reserved D1 /COL D2 /REC D3 /PART D4 Reserved D5 Reserved ...
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LERIC8 Registers (Continued) 6.4 PORTS 1-8 (10BASE-T) STATUS/CONFIGURATION REGISTERS Address: RA4 - RA0 0 0010 to 0 1001 - lower nibble 1 0010 to 1 1001 - upper nibble Bit Bit Name Access D0 /GDLNK D1 /COL D2 /REC ...
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System Considerations The DP83959 can be designed into several types of repeat- ers. The most common design is the unmanaged, stand-alone, 8-port repeater, where a single LERIC8 will be used to provide the repeater capabilities. For designs that re- ...
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DC Specifications Absolute Maximum Ratings Supply Voltage ( Input Voltage (V ) -0. Output Voltage (V ) -0. OUT Power Dissipation ( Storage Temperature Range (T ) STG ...
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Switching Characteristics 9.1 PORT ARBITRATION / Number Symbol T1 ackilackol /ACKI Low to /ACKO Low T2 ackihackoh /ACKI High to /ACKO High Note: Timing valid with no receive or ...
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Switching Characteristics 9.3 RECEIVE - 10BASE-T PORTS Receive activity propagation start up and end delays for 10BASE-T ports T5t / T3t / Number Symbol T3t rxaackol RX Active to ...
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Switching Characteristics 9.5 TRANSMIT - 10BASE-T PORTS Receive activity propagation start up and end delays 10BASE-T ports. CLOCK T16 T15 Number Symbol T15t actnltxa /ACTN Low to TX Active T16t ...
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Switching Characteristics 9.6.2 Receive Collisions C D T32 Number Symbol T32a cdacolna CD Active to /COLN Low T33a cdicolni CD Inactive to /COLN High T39 colnljs /COLN Low to Start of ...
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Switching Characteristics 9.8 COLLISION - ALL PORTS - INTER-LERIC BUS / Number Symbol T34 anylmin /ANYXN Low time T35 anyhtxai /ANYXN High all Inactive ...
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Switching Characteristics 9.10 RESET / MLOAD ** / MLOAD_INT /MLOAD_INT is the internal signal which is delayed 5 cycles from the external /MLOAD signal Number Symbol T61 ...
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Switching Characteristics 9.12 REGISTER READ / T89 RA( 4:0 ) (address (data Number Symbol T80 rdadrs Address Setup from /BUFEN Low T81 rdadrh Address ...
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Switching Characteristics 9.13 REGISTER WRITE / T99 RA( 4:0 ) (address) D( 3:0 ) (data Number Symbol T90 wradrs Address Setup from /BUFEN Low T91 wradrh Address Hold ...
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Switching Characteristics 9.14 INTER-LERIC BUS (PACKET OUTPUT T105 // / T106 Number Symbol T101 ircoh IRC Output Duty Cycle High Time T102 ...
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AC Timing Test Conditions 10.1 GENERAL TEST CONDITIONS All AUI specifications are valid only if the mandatory isolation transformer is employed and all differential signals are mea- sured at the AUI connector (not at the DP83959 LERIC8 di- rectly). ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time without notice, to change said circuitry or specification. inches (millimeters) unless otherwise noted Molded Plastic Quad Flat Package, JEDEC Order Number DP83959VUL NS Package Number VUL160A 2. A critical component is any component of a life support ...