AD5932YRUZ Analog Devices Inc, AD5932YRUZ Datasheet - Page 6

• Manufacturer Part Number: AD5932YRUZ
• Description: IC PROG WAVEFORM GEN SNGL16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5932YRUZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 24 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Synthesizer Type: Frequency
• Frequency: 25MHz
• Supply Voltage Range: 2.3V To 5.5V
• Supply Current: 2.4mA
• Operating Temperature Range: -40°C To +125°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5932
TIMING SPECIFICATIONS
All input signals are specified with t
Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications T
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
MASTER CLOCK AND TIMING DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Guaranteed by design, not production tested.
1
Limit at T
20
8
8
25
10
10
5
10
5
3
2 × t
0
10 × t
8 × t
1 × t
2 × t
20
FSYNC
SDATA
SCLK
1
1
1
1
1
MIN
, T
MAX
R
t
= t
7
D15
F
= 5 ns (10% to 90% of V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns max
D14
t
6
t
5
Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high time
SCLK low time
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
Minimum CTRL pulse width
CTRL rising edge to VOUT delay (initial pulse, includes initialization)
CTRL rising edge to VOUT delay (initial pulse, includes initialization)
Frequency change to SYNC output, each frequency increment
Frequency change to SYNC output, end of scan
MCLK falling edge to MSBOUT
CTRL rising edge to MCLK falling edge setup time
MCLK
Figure 4. Serial Timing
Figure 3. Master Clock
Rev. 0 | Page 6 of 28
D2
DD
t
2
t
) and are timed from a voltage level of (V
t
4
1
t
t
3
9
D1
t
10
MIN
to T
D0
t
8
MAX
, unless otherwise noted.
D15
IL
+ V
IH
D14
)/2 (see Figure 3 to