AD9958BCPZ Analog Devices Inc, AD9958BCPZ Datasheet - Page 6

• Manufacturer Part Number: AD9958BCPZ
• Description: IC DDS DUAL 500MSPS DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9958BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
• Resolution (bits): 10 b
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Pll Type: Frequency Synthesis
• Frequency: 500MHz
• Supply Current: 105mA
• Supply Voltage Range: 1.71V To 1.89V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9958/PCBZ - BOARD EVALUATION FOR AD9958
• Lead Free Status / Rohs Status: Compliant

AD9958
Parameter
SERIAL PORT TIMING CHARACTERISTICS
MISCELLANEOUS TIMING CHARACTERISTICS
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS
Residual Phase Noise @ 40.1 MHz (f
Residual Phase Noise @ 75.1 MHz (f
Residual Phase Noise @ 100.3 MHz (f
Maximum Frequency Serial Clock (SCLK)
Minimum SCLK Pulse Width Low (t
Minimum SCLK Pulse Width High (t
Minimum Data Setup Time (t
Minimum Data Hold Time
Minimum CS Setup Time (t
Minimum Data Valid Time for Read Operation
MASTER_RESET Minimum Pulse Width
I/O_UPDATE Minimum Pulse Width
Minimum Setup Time (I/O_UPDATE to SYNC_CLK)
Minimum Hold Time (I/O_UPDATE to SYNC_CLK)
Minimum Setup Time (Profile Inputs to SYNC_CLK)
Minimum Hold Time (Profile Inputs to SYNC_CLK)
Minimum Setup Time (SDIO Inputs to SYNC_CLK)
Minimum Hold Time (SDIO Inputs to SYNC_CLK)
Propagation Time Between REF_CLK and SYNC_CLK
Profile Pin Toggle Rate
V
V
Logic 1 Current
Logic 0 Current
Input Capacitance
V
V
Residual Phase Noise @ 15.1 MHz (f
IH
IL
OH
OL
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Multiplier Enabled 20×
PRE
DS
)
)
PWL
OUT
OUT
OUT
PWH
OUT
)
) with REFCLK
) with REFCLK
) with REFCLK
)
) with REFCLK
Min
1.6
2.2
2.2
0
1.0
12
1
1
4.8
0
5.4
0
2.5
0
2.25
2.0
2.7
Rev. A | Page 6 of 44
Typ
−139
−132
−125
−121
3.5
2
−127
−136
−138
−117
−128
−130
−110
−121
−123
−107
−119
−119
3
−12
Max
200
5.5
2
0.8
12
0.4
Unit
ns
ns
V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Sync
clocks
V
V
μA
μA
pF
V
Test Conditions/Comments
Min pulse width = 1 sync clock period
Min pulse width = 1 sync clock period
Rising edge to rising edge
Rising edge to rising edge
1 mA load