AD9830ASTZ Analog Devices Inc, AD9830ASTZ Datasheet - Page 3

• Manufacturer Part Number: AD9830ASTZ
• Description: IC DDS 10BIT 50MHZ CMOS 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9830ASTZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Pll Type: Direct Digital Synthesis
• Frequency: 50MHz
• Supply Current: 60mA
• Supply Voltage Range: 4.75V To 5.25V
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Direct Digital Synthesizer
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Bandwidth: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD9830EBZ - BOARD EVALUATION AD9830
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. A
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
Guaranteed by design, but not production tested.
1
2
3
4
4A
5
6
7
8
9
9A
10
See Pin Description section.
1
1
1
1
A0, A1, A2
MCLK
WR
DATA
PSEL0, PSEL1
Limit at
T
(A Version)
20
8
8
8
8
8
t
5
3
8
8
t
WR
1
1
MIN
FSELECT
RESET
MCLK
to T
MAX
t
4A
VALID DATA
t
2
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Figure 3. Writing to a Phase/Frequency Register
(V
t
1
DD
= +5 V
t
Figure 2. WR –MCLK Relationship
3
t
Figure 4. Control Timing
5
5%; AGND = DGND = 0 V, unless otherwise noted)
VALID DATA
t
t
9
7
Test Conditions/Comments
MCLK Period
MCLK High Duration
MCLK Low Duration
WR Rising Edge Before MCLK Rising Edge
WR Rising Edge After MCLK Rising Edge
WR Pulse Width
Duration Between Consecutive WR Pulses
Data/Address Setup Time
Data/Address Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
RESET Pulse Duration
t
6
t
10
t
VALID DATA
8
–3–
t
6
t
9A
t
5
VALID DATA
t
4
VALID DATA
AD9830